Semiconductor device

ABSTRACT

The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2013-110476 filed onMay 27, 2013 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device, and ispreferably applicable to, for example, a semiconductor device having acapacitive element.

In, some semiconductor devices, a microcomputer is formed in onesemiconductor chip. In the semiconductor chip including a microcomputerformed therein, there are formed a Central Processing Unit: CPUincluding logic circuits such as a CMISFET (Complementary MetalInsulator Semiconductor Field Effect Transistor), memories, analogcircuits, or the like.

As the memory used in the semiconductor chip, for example, anelectrically rewritable nonvolatile memory is used. As the electricallyerasable/writable nonvolatile memory (nonvolatile semiconductor storagedevice), an EEPROM (Electrically Erasable and Programmable Read OnlyMemory) or a flash memory has been widely used.

In order to operate the nonvolatile memory as described above, a drivingcircuit such as a booster circuit is formed in a semiconductor chip. Thedriving circuit requires a high-precision capacitive element. Further,in the semiconductor chip including a microcomputer formed therein, ananalog circuit is also formed. The analog circuit also requires ahigh-precision capacitive element. Therefore, in the semiconductor chip,capacitive elements are also formed other than the nonvolatile memoryand the MISFET.

Some such capacitive elements are formed simultaneously with thenonvolatile memory cell using a step of manufacturing the nonvolatilememory cell. Specifically, in the step of forming the control gateelectrode of a nonvolatile memory cell, the lower electrode of thecapacitive element is formed. In the step of forming a lamination filmincluding a charge accumulation film of the nonvolatile memory, thecapacitive insulation film of the capacitive element is formed. Then, inthe step of forming the memory gate electrode of the nonvolatile memorycell, the upper electrode of the capacitive element is formed. Thecapacitive element is called a PIP (Polysilicon Insulator Polysilicon)capacitive element because a polysilicon film is used for the upperelectrode and the lower electrode.

In Japanese. Unexamined Patent Publication No. 2009-99640 (PatentDocument 1) and Japanese Unexamined Patent Publication No. 2011-40621(Patent Document 2), there is disclosed a PIP capacitive element havinga lower electrode and an upper electrode each formed of a polysiliconfilm formed over a semiconductor substrate, and a capacitive insulationfilm formed of, for example, a silicon oxide film, formed between thelower electrode and the upper electrode.

The Patent Document 1 discloses the following: in the upper electrode,there are an overlapping region whose underlying layer includes thelower electrode present therein, and a non-overlapping region whoseunderlying layer includes no lower electrode present therein; and theplug to be coupled with the upper electrode is formed in thenon-overlapping region of the upper electrode. Whereas, the PatentDocument 2 discloses the following: the lower electrode, the capacitivefilm and the upper electrode are stacked in this order; and a via iscoupled with the upper electrode over the lower electrode.

PATENT DOCUMENT

[Patent Document 1]

Japanese Unexamined Patent Publication No. 2009-99640

[Patent Document 2]

Japanese Unexamined Patent Publication No. 2011-40621

SUMMARY

For example, in the PIP capacitive element described in the PatentDocument 1, the upper electrode has a step region between theoverlapping region and the non-overlapping region; and the plug to becoupled with the upper electrode is coupled with the upper electrode inthe non-overlapping region. Whereas, over the surface f the upperelectrode, a metal silicide film is formed. In the step region, asidewall formed of an insulation film is formed at the sidewall of theupper electrode. Over the surface of the upper electrode in the stepregion, no metal silicide film is formed. Accordingly, the upperelectrode in the step region has a high resistance. The plug to becoupled with the upper electrode in the non-overlapping region cannot beelectrically coupled with the portion of the upper electrode present inthe overlapping region at a low resistance. For this reason, the plugand the upper electrode cannot be electrically coupled at a lowresistance.

On the other hand, for example, in the PIP capacitive element describedin the Patent Document 2, the plug to be coupled with the upperelectrode is coupled with the upper electrode in the overlapping region.Whereas, entirely over the surface of the upper electrode, a metalsilicide film is formed. Accordingly, the plug and the upper electrodecan be electrically coupled at a low resistance.

However, in such a PIP capacitive element, the thickness of thecapacitive element is the sum of the thickness of the upper electrode,the thickness of the capacitive insulation film, and the thickness ofthe lower electrode. For this reason, the height position of the topsurface of the capacitive element is higher than, for example, theheight position of the top surface of the source region or the drainregion in a nonvolatile memory cell. Namely, the distance in thethickness direction from the bottom surface of the wire over thecapacitive element to the top surface of the upper electrode of thecapacitive element is shorter than the distance in the thicknessdirection from the bottom surface of the wire over the nonvolatilememory cell to the top surface of the source region or the drain region.

Accordingly, when the contact hole penetrating through the interlayerinsulation film, and reaching the source electrode or the drainelectrode, and the contact hole penetrating through the interlayerinsulation film, and reaching the top surface of the upper electrode ofthe capacitive element are formed in the same step, the contact hole maypenetrate through the interlayer insulation film, the upper electrode,and the capacitive insulation film, to reach the lower electrode. Insuch a case, the plug formed of a conductive film embedded in thecontact hole may cause a short circuit between the upper electrode andthe lower electrode, resulting in the degradation of the performances ofthe semiconductor device.

Other objects and novel features will be apparent from the descriptionof this specification and the accompanying drawings.

In accordance with one embodiment, a semiconductor device has a firstelectrode and a dummy electrode formed apart from each other over asemiconductor substrate, a second electrode formed between the firstelectrode and the dummy electrode, at the circumferential side surfaceof the first electrode, and at the circumferential side surface of thedummy electrode, and a capacitive insulation film formed between thefirst electrode and the second electrode. The first electrode, thesecond electrode, and the capacitive insulation film form a capacitiveelement. Further, the semiconductor device has a first plug penetratingthrough the interlayer insulation film, and electrically coupled withthe first electrode, and a second plug penetrating through theinterlayer insulation film, and electrically coupled with a portion ofthe second electrode formed at a side surface of the dummy electrodeopposite to the first electrode side.

Further, in accordance with another embodiment, a semiconductor devicehas a first electrode formed over a semiconductor substrate, an openingpenetrating through the first electrode, a second electrode formed inthe inside of the opening, and at the circumferential side surface ofthe first electrode, and a capacitive insulation film formed between thefirst electrode and the second electrode. The first electrode, thesecond electrode, and the capacitive insulation film form a capacitiveelement. Still further, the semiconductor device has a first plugpenetrating through the interlayer insulation film, and electricallycoupled with the first electrode, and a second plug penetrating thoughthe interlayer insulation film, and electrically coupled with the secondelectrode.

In accordance with a still other embodiment, a semiconductor device hasa first electrode formed over a semiconductor substrate, a secondelectrode formed at the circumferential side surface of the firstelectrode, and a capacitive insulation film formed between the firstelectrode and the second electrode. The first electrode includes aplurality of first line parts respectively extending in a firstdirection, and arrayed in a second direction crossing with the firstdirection in plan view. The first electrode, the second electrode, andthe capacitive insulation film form a capacitive element. Further, thesemiconductor device has a first plug penetrating through the interlayerinsulation film, and electrically coupled with the first electrode, anda second plug penetrating through the interlayer insulation film, andelectrically coupled with the second electrode.

In accordance with one embodiment, it is possible to improve theperformances of the semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view showing a semiconductor chip as a semiconductordevice of First Embodiment;

FIG. 2 is a plan view showing a capacitive element in First Embodiment;

FIG. 3 is a cross sectional view showing the capacitive element in FirstEmbodiment;

FIG. 4 is a plan view showing a capacitive element in a first modifiedexample of First Embodiment;

FIG. 5 is a cross sectional view showing the capacitive element in thefirst modified example of First Embodiment;

FIG. 6 is a cross sectional view showing a capacitive element in a stillother example;

FIG. 7 is a plan view showing a capacitive element in a second modifiedexample of First Embodiment;

FIG. 8 is a cross sectional view showing the capacitive element in thesecond modified example of First Embodiment;

FIG. 9 is a cross sectional view showing the capacitive element in thesecond modified example of First Embodiment;

FIG. 10 is a plan view showing a capacitive element in a third modifiedexample of First Embodiment;

FIG. 11 is a cross sectional view showing the capacitive element in thethird modified example of First Embodiment;

FIG. 12 is a cross sectional view showing the semiconductor device ofFirst Embodiment;

FIG. 13 is a cross sectional view showing the semiconductor device ofFirst Embodiment;

FIG. 14 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 15 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 16 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 17 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 18 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 19 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 20 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 21 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 22 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 23 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 24 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 25 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 26 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 27 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 28 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 29 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 30 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 31 is a cross sectional view of the semiconductor device during amanufacturing step in First Embodiment;

FIG. 32 is a cross sectional view showing a semiconductor device ofComparative Example 1;

FIG. 33 is a cross sectional view showing a semiconductor device ofComparative Example 2;

FIG. 34 is a plan view showing a capacitive element in SecondEmbodiment;

FIG. 35 is a cross sectional view showing the capacitive element inSecond Embodiment;

FIG. 36 is a plan view showing a capacitive element in a first modifiedexample of Second Embodiment;

FIG. 37 is a cross sectional view showing the capacitive element in thefirst modified example of Second Embodiment;

FIG. 38 is a plan view showing a capacitive element in a still otherexample;

FIG. 39 is a cross sectional view showing a capacitive element in astill other example;

FIG. 40 is a cross sectional view showing a capacitive element in astill other example;

FIG. 41 is a plan view showing a capacitive element in a second modifiedexample of Second Embodiment;

FIG. 42 is a cross sectional view showing the capacitive element in thesecond modified example of Second Embodiment;

FIG. 43 is a plan view showing a capacitive element in Third Embodiment;

FIG. 44 is a plan view showing a capacitive element in a first modifiedexample of Third Embodiment;

FIG. 45 is a plan view showing a capacitive element in a second modifiedexample of Third Embodiment;

FIG. 46 is a cross sectional view showing the capacitive element in thesecond modified example of Third Embodiment; and

FIG. 47 is a cross sectional view showing a capacitive element in FourthEmbodiment.

DETAILED DESCRIPTION

In the following embodiment, the embodiment may be described in aplurality of divided sections or embodiments for convenience, ifrequired. However, unless otherwise specified, these are not independentof each other, but are in a relation such that one is a modifiedexample, details, complementary explanation, or the like of a part orthe whole of the other.

Further, in the following embodiments, when a reference is made to thenumber of elements, and the like (including number, numerical value,quantity, range, or the like), the number of elements is not limited toa specific number, but may be greater than or less than the specificnumber, unless otherwise specified, and except the case where the numberis apparently limited to the specific number in principle, and othercases.

Further, in the following embodiments, it is needless to say that theconstitutional elements (including element steps, or the like) are notalways essential, unless otherwise specified, except the case where theyare apparently considered essential in principle, and other cases.Similarly, in the following embodiments, when a reference is made to theshapes, positional relationships, or the like of the constitutionalelements, or the like, it is understood that they include onessubstantially analogous or similar to the shapes or the like, unlessotherwise specified, unless otherwise considered apparently inprinciple, and except for other cases. This also applies to theforegoing numerical values and ranges.

Below, representative embodiments will be described in details byreference to the accompanying drawings. Incidentally, in all thedrawings for describing the embodiments, the members having the samefunction are given the same reference signs and numerals, and a repeateddescription thereon is omitted. Further, in the following embodiments, adescription on the same or similar parts will not be repeated inprinciple, unless particularly required.

Further, in drawings to be used in embodiments, hatching may be omittedfor ease of understanding of the drawings even in a cross-sectionalview. Whereas, for ease of understanding of the drawings, hatching maybe provided even in a plan view

Further, in a cross sectional view and a plan view, the size of eachpart does not correspond to that of an actual device. For ease ofunderstanding of the drawings, a specific part may be shown on arelatively enlarged scale. Whereas, even when a plan view and a crosssectional view correspond to each other, respective parts may be shownon different scales.

First Embodiment

<Configuration of Semiconductor Device>

FIG. 1 is a plan view showing a semiconductor chip as a semiconductordevice of First Embodiment. FIG. 1 shows the layout configuration ofrespective elements formed at a semiconductor chip CHP as, for example,a semiconductor device having a microcomputer formed therein.

In FIG. 1, the semiconductor chip CHP as a semiconductor device has aCPU1, a RAM (Random Access Memory) 2, an analog circuit 3, and a flashmemory 4. Then, in the peripheral part of the semiconductor chip, thereare formed pads PD which are input/output external terminals forcoupling the circuits and external circuits.

The CPU1 is also called a central processing unit, and corresponds tothe heart of a computer or the like. The CPU1 reads and decodes aninstruction from a storage device, and performs diverse operations andcontrols based on that, and hence is required to have a high processingspeed performance. Therefore, the MISFET (Metal Insulator SemiconductorField Effect Transistor) forming the CPU1 requires a relatively largercurrent driving force among the elements formed in the semiconductorchip CHP. Namely, the MISFET forming the CPU1 is formed of a lowbreakdown voltage MISFET.

The RAM2 is a memory capable of reading memory information at random,namely, stored memory information randomly, and newly writing memoryinformation, and is also called a random access memory. The RAMs as IC(Integrated Circuit) memories include two kinds of a DRAM (Dynamic RAM)using a dynamic circuit, and a SRAM (Static RAM) using a static circuit.The DRAM is a random write/read memory requiring a storage retainingoperation; and the SRAM is a random write/read memory not requiring astorage retaining operation. The RAM2 is required to have a high speedperformance of operation. For this reason, the MISFET forming the RAM2requires a relatively larger current driving force among the elementsformed in the semiconductor chip CHP. Namely, as the MISFET forming theRAM2, there is used a low breakdown voltage MISFET.

The analog circuit 3 is a circuit handling temporally continuouslychanging voltage or current signals, namely, analog signals, and isformed of, for example, an amplification circuit, a conversion circuit,a modification circuit, an oscillation circuit, or a power supplycircuit. As the MISFET forming the analog circuit 3, there is used arelatively higher breakdown voltage MISFET among elements formed at thesemiconductor chip CHP.

The flash memory 4 is one kind of nonvolatile memories capable ofelectric rewriting for both a write operation and an erase operation,and is also called an electrically erasable programmable read-onlymemory. The memory cells of the flash memory 4 include a memory cellselecting MISFET, and, for example, a MONOS (Metal Oxide Nitride OxideSemiconductor) type FET (Field Effect Transistor) for storage. For thewrite operation of the flash memory, there is used hot electroninjection or Fowler-Nordheim Tunneling phenomenon; and for the eraseoperation, there is used Fowler-Nordheim Tunneling phenomenon or hothole injection.

In order to operate the flash memory 4 as described above, a drivingcircuit such as a booster circuit is formed in the semiconductor chipCHP. The driving circuit requires a high-precision capacitive element.Further, the analog circuit 3 also requires a high-precision capacitiveelement. Therefore, in the semiconductor chip CHP, capacitive elementsare also formed other than the nonvolatile memory 4 and MISFETs. Thepresent First Embodiment has one feature in the structure of thecapacitive element as the PIP capacitive element formed in thesemiconductor chip CHP. Below, a description will be given to theconfiguration of the capacitive element as the PIP capacitive elementformed in the semiconductor chip CHP. Incidentally, below, the PIPcapacitive element will be simply referred to as a capacitive element.

<Configuration of Capacitive Element>

FIG. 2 is a plan view showing a capacitive element in First Embodiment.FIG. 3 is a cross sectional view showing the capacitive element in FirstEmbodiment. FIG. 3 is a cross sectional view along line A-A of FIG. 2.

Incidentally, the plan view of FIG. 2 is a plan perspective view of thecapacitive element as seen through wires HL1 and HL2, an interlayerinsulation film 34, and a sidewall 29 b (see FIG. 3), and also does notshow the semiconductor substrate 10 and the element isolation region 11(the same also applies to the following plan views). Whereas, in theplan view of FIG. 2, for ease of understanding, other portions than anelectrode 23 are hatched, but the electrode 23 is not hatched (the samealso applies to the following plan views).

As shown in FIGS. 2 and 3, the semiconductor device has semiconductorsubstrate 10 and the element isolation region 11. The element isolationregion 11 is formed in the front surface (first main surface) 10 a ofthe semiconductor substrate 10. The semiconductor substrate 10 is formedof, for example, silicon (Si) single crystal. The element isolationregion 11 is formed of, for example, a silicon oxide film.

The semiconductor device has an electrode 16 formed of a conductive filmCF1 formed over the element isolation region 11. Preferably, theelectrode 16 is formed of the conductive film CF1 formed over theelement isolation region 11, and a metal silicide film 33 formed at thesurface of the conductive film CF1. The conductive film CF1 is formedof, for example, a polysilicon film. The metal silicide film 33 isformed of, for example, a cobalt silicide film. Further, as shown inFIG. 3, the electrode 16 may be formed over the element isolation region11 via an insulation film IF1.

As shown in FIG. 2, the electrode 16 includes a plurality of line partsLP1 and a line part LP2. The plurality of line parts LP1 respectivelyextend in the Y axis direction, and are arrayed in the X axis direction,where the X axis direction and the Y axis direction are two directionsmutually crossing in plan view. The line part LP2 extends in the X axisdirection, and is coupled with the ends on one side of the plurality ofline parts LP1 in the Y axis direction in plan view. With such aconfiguration, the plurality of line parts LP1 are electrically coupledto one another via the line part LP2. The electrode 16 including theplurality of line parts LP1 and the line part LP2 has a comb-like shapein plan view.

Incidentally, in the present specification, the wording “in plan view”means the view seen from the direction perpendicular to the frontsurface 10 a of the semiconductor substrate 10.

Further, the semiconductor device has a dummy electrode DE formed of aconductive film CF1 formed apart from the electrode 16 over the elementisolation region 11. Preferably, the dummy electrode DE is formed of theconductive film CF1 at the same layer as the conductive film CF1 formingthe electrode 16, and the metal silicide film 33 formed at the surfaceof the conductive film CF1. As described previously, the conductive filmCF1 is formed of, for example, a polysilicon film. The metal silicidefilm 33 is formed of, for example, a cobalt silicide film. Further, asshown in FIG. 3, the dummy electrode DE may be formed over the elementisolation region 11 via the insulation film IF1.

As shown in FIG. 2, in plan view, the dummy electrode DE extends in theX axis direction, and is arranged opposite to the line part LP2 acrossthe plurality of line parts LP1, namely, on the side of the plurality ofline parts LP1 opposite to the line part LP2 side. In other words, thedummy electrode DE is arranged on each one side of the plurality of lineparts LP1 in the X axis direction, and the line part LP2 is coupled toeach end on the other side of the plurality of line parts LP1 in the Xaxis direction.

Further, the semiconductor device has an electrode 23 formed of aconductive film CF2 integrally formed between the electrode 16 and thedummy electrode DE, at the circumferential side surface of the electrode16, and the circumferential side surface of the dummy electrode DE.Preferably, the electrode 23 is formed of the conductive film CF2integrally formed between the electrode 16 and the dummy electrode DE,at the circumferential side surface of the electrode 16, and thecircumferential side surface of the dummy electrode DE, and a metalsilicide film 33 formed over the surface of the conductive film CF2. Theconductive film CF2 is formed of, for example, a polysilicon film. Themetal silicide film 33 is formed of, for example, a cobalt silicidefilm.

Further, the semiconductor device has a capacitive insulation film 27formed of an insulation film IF2 formed between the electrode 16 and theelectrode 23, and between the electrode 23 and the semiconductorsubstrate 10. Therefore, the electrode 23 is formed at thecircumferential side surface of the electrode 16, and thecircumferential side surface of the dummy electrode DE via thecapacitive insulation film 27. Then, the electrode 16, the electrode 23,and the capacitive insulation film 27 form the capacitive element.Incidentally, in the outer circumferential part of the capacitiveelement, a sidewall 29 b formed of an insulation film is formed at thecircumferential side surface of the electrode 23. The metal silicidefilm 33 is formed entirely over the surface of the electrode 23 exceptfor the region including the sidewall 29 b formed therein.

As shown in FIG. 3, over the element isolation region 11, an interlayerinsulation film 34 is formed in such a manner as to cover the capacitiveelement formed of the electrode 16, the electrode 23, and the capacitiveinsulation film 27. In the interlayer insulation film 34, there areformed a contact hole CH1 and a contact hole CH2 as coupling holes. Thecontact hole CH1 penetrates through the interlayer insulation film 34,and reaches the electrode 16. The contact hole CH2 penetrates throughthe interlayer insulation film 34, and reaches the electrode 23.

In the contact hole CH1, there is formed a plug PG1 as a couplingelectrode formed of a conductive film embedded in the contact hole CH1,and electrically coupled with the electrode 16. Whereas, in the contacthole CH2, there is formed a plug PG2 as a coupling electrode formed of aconductive film embedded in the contact hole CH2, and electricallycoupled with the electrode 23. Over the plug PG1, there is formed a wireHL1 electrically coupled with the plug PG1. Over the plug PG2, there isformed a wire HL2 electrically coupled with the plug PG2. Over thesurface of the electrode 16, there is formed the metal silicide film 33.Accordingly, the plug PG1 is in contact with the metal silicide film 33exposed at the bottom of the contact hole CH1, and is electricallycoupled with the electrode 16. Whereas, over the surface of theelectrode 23, the metal silicide film 33 is formed. Accordingly, theplug PG2 is in contact with the metal silicide film 33 exposed at thebottom of the contact hole CH2, and is electrically coupled with theelectrode 23.

The contact hole CH1 penetrates through the interlayer insulation film34, and reaches the line part LP2 of the electrode 16. The plug PG1 isformed of a conductive film embedded in the contact hole CH1, and iselectrically directly coupled with the line part LP2 of the electrode16.

The contact hole CH2 penetrates through the interlayer insulation film34, and reaches the portion of the electrode 23 formed at the sidesurface of the dummy electrode DE opposite to the electrode 16 side.With such a configuration, the plug PG2 can be electrically coupled withany portion of the electrode 23 via the metal silicide film 33 having arelatively smaller electric resistance formed over the surface of theelectrode 23. Further, entirely over the surface of the electrode 23,there is formed the metal silicide film 33. Accordingly, the plug PG2can be electrically coupled with any portion of the electrode 23 at alow resistance.

Whereas, the electrode 16 and the electrode 23 are formed in differentregions in plan view. In other words, there is no overlapping regionwhere the electrode 16 and the electrode 23 overlap each other in planview. Such a configuration eliminates the possibility that the contacthole CH2 penetrates through the electrode 23 and reaches the electrode16. This can prevent an electric short circuit between the electrode 16and the electrode 23 via the plug PG2.

Further, the electrode 16 has the plurality of line parts LP1. Thisresults in an increase in area of the side surface of the electrode 23opposite to the side surface of the electrode 16. For this reason, it ispossible to increase the capacity of the capacitive element with ease.

On the other hand, as shown in FIG. 3, the dummy electrode DE is in astate electrically insulated from the electrode 16. For this reason, thecontact hole CH2 may reach the dummy electrode DE. Namely, the contacthole CH2 may have a portion overlapping the dummy electrode DE in planview. As a result, even when the film thickness of the conductive filmCF2 forming the electrode 23 is small, and the width of the electrode 23formed at the side surface of the electrode 16 is small, the contacthole CH2 may be shifted to the dummy electrode DE side. For this reason,the contact hole CH2 can be aligned with ease.

FIRST MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 4 is a plan view showing a capacitive element in a first modifiedexample of First Embodiment; and FIG. 5 is across sectional view showingthe capacitive element in the first modified example of FirstEmbodiment. FIG. 5 is a cross sectional view along line A-A of FIG. 4.

The capacitive element in the present first modified example isdifferent from the capacitive element in First Embodiment described byreference to FIGS. 2 and 3 in that the line part LP2 (see FIG. 2) is notdisposed, and in that a plurality of plugs PG1 are electrically directlycoupled with a plurality of line parts LP1, respectively, and further,in that, in addition to the plugs PG2, a plurality of plugs PG3 areelectrically directly coupled with the electrode 23. The capacitiveelement in the present first modified example is the same as thecapacitive element in First Embodiment in other respects.

As shown in FIG. 4, the electrode 16 includes a plurality of line partsLP1, but does not include a line part LP2. Further, as with FirstEmbodiment, the plurality of line parts LP1 respectively extend in the Yaxis direction, and are arrayed in the X axis direction in plan view.Accordingly, the plurality of line parts LP1 are formed apart from oneanother.

The contact hole CH1 penetrates through the interlayer insulation film34, and reaches the line part LP1 of the electrode 16. The plug PG1 isformed of a conductive film embedded in the contact hole CH1, and iselectrically directly coupled with the line part LP1 of the electrode16.

In the interlayer insulation film 34, contact holes CH3 as openings areformed in addition to the contact holes CH1 and CH2. The contact holesCH3 penetrate through the interlayer insulation film 34, and reach theportion of the electrode 23 arranged between the adjacent line partsLP1. In the contact hole CH3, there is formed a plug PG3 as a couplingelectrode formed of a conductive film embedded in the contact hole CH3,and electrically coupled with the portion of the electrode 23 arrangedbetween the adjacent line parts LP1. Over the plug PG3, there is formeda wire HL3 electrically coupled with the plug PG3.

Also in the present first modified example, as with First Embodiment,the plug PG2 can be electrically coupled with any portion of theelectrode 23 at a low resistance. Accordingly, the electrode 16 and theelectrode 23 can be prevented from being electrically short-circuitedwith each other. Thus, the capacity of the capacitive element can beincreased with ease, and the contact hole CH2 can be aligned with ease.

On the other hand, in the present first modified example, as comparedwith First Embodiment, although the width of the line part LP1 in the Xaxis direction is larger, the plug PG1 can be electrically directlycoupled with the line part LP1. For this reason, the plug PG1 can beelectrically coupled with the electrode 16 at a still lower resistance.

Incidentally, FIG. 6 shows a capacitive element of a still other examplein a cross sectional view. As shown in FIG. 6, when the conductive filmCF1 is patterned, thereby to form the line parts LP1, the opening OP1formed between the adjacent line parts LP1 is prevented from penetratingthrough the conductive film CF1. This allows the bottoms of theplurality of line parts LP1 to be combined with one another via theconductive film CF1. Namely, the electrode 16 includes coupling partsCN1 coupling the bottoms of the adjacent line parts LP1.

In the example shown in FIG. 6, when the height position of the topsurface of the electrode 23 is set equal to that in the example shown inFIG. 5, the height position of the bottom surface of the electrode 23becomes higher, resulting in a reduction of the thickness of theelectrode 23. For this reason, the capacity of the capacitive elementdecreases. However, the line parts LP1 are coupled with one another attheir respective bottoms. For this reason, the electric resistance ofthe electrode 16 can be reduced. However, it is preferable that theelectrode 16 and the dummy electrode DE are in a state electricallyinsulated from each other. For this reason, the bottoms of the adjacentline parts LP1 may be combined with one another. However, it ispreferable that the bottom of the electrode 16 and the bottom of thedummy electrode DE are prevented from being combined with each other.

Incidentally, thus, when the conductive film CF1 is patterned, theopening OP1 is prevented from penetrating through the conductive filmCF1. This is also applicable to respective embodiments including theFirst Embodiment, and respective modified examples of the embodimentsother than the first modified example of First Embodiment.

SECOND MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 7 is a plan view showing a capacitive element in a second modifiedexample of First Embodiment. FIGS. 8 and 9 are each a cross sectionalview showing the capacitive element in the second modified example ofFirst Embodiment. FIG. 8 is a cross sectional view along line A-A ofFIG. 7. FIG. 9 is a cross sectional view along line B-B of FIG. 7.

The capacitive element of the present second modified example isdifferent from the capacitive element of First Embodiment described byreference to FIGS. 2 and 3 in that the electrode 23 is formed not onlybetween the electrode 16 and the dummy electrode DE, at thecircumferential side surface of the electrode 16, and thecircumferential side surface of the dummy electrode DE, but also in apartial region of the top surface of the electrode 16. The capacitiveelement of the present second modified example is the same as thecapacitive element of First Embodiment in other respects.

As shown in FIG. 7, the electrode 16 does not include a line part, and,in plan view, has a rectangular shape, and is integrally formed.Incidentally, in the present second modified example, the dummyelectrode DE extends in the Y axis direction, and is formed apart fromthe electrode 16 in the X axis direction.

The electrode 23 is also formed in a partial region of the top surfaceof the electrode 16 in addition to between the electrode 16 and thedummy electrode DE, at the circumferential side surface of the electrode16, and the circumferential side surface of the dummy electrode DE.Whereas, the electrode 23 may be integrally formed. Further, at the sidesurface of the portion of the electrode 23 formed over the top surfaceof the electrode 16, there is formed a sidewall 29 c formed of ainsulation film. Incidentally, FIG. 7 shows the state as seen throughthe sidewall 29 c.

The metal silicide film 33 is formed in a region of the top surface ofthe electrode 16 in which neither of the electrode 23 and the sidewall29 c is formed therein. Further, the contact hole CH1 penetrates throughthe interlayer insulation film 34, and reaches the region of the topsurface of the electrode 16 in which neither of the electrode 23 andsidewall 29 c is formed. The plug PG1 is formed of a conductive filmembedded in the contact hole CH1, and is electrically directly coupledwith the electrode 16. The contact hole CH2 and the plug PG2 are thesame as those in First Embodiment.

Also in the present second modified example, as with First Embodiment,the plug PG2 can be electrically coupled with any portion of theelectrode 23 at a low resistance. Accordingly, the electrode 16 and theelectrode 23 can be prevented from being electrically short-circuited.Thus, the contact hole CH2 can be aligned with ease.

On the other hand, in the present second modified example, as comparedwith First Embodiment, the area of the side surface of the electrode 23opposite to the side surface of the electrode 16 may be reduced.However, the top surface of the electrode 16 and the bottom surface ofthe electrode 23 are opposite to each other. For this reason, thecapacity of the capacitive element can be increased with ease.

THIRD MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 10 is a plan view showing a capacitive element in a third modifiedexample of First Embodiment. FIG. 11 is a cross sectional view showingthe capacitive element in the third modified example of FirstEmbodiment. FIG. 11 is a cross sectional view along line A-A of FIG. 10.

The capacitive element of the present third modified example isdifferent from the semiconductor device of First Embodiment described byreference to FIGS. 2 and 3 in that a cap insulation film CP1 is formedin a partial region of the top surface of the electrode 16. Thecapacitive element of the present third modified example is the same asthe capacitive element of First Embodiment in, other respects.

As shown in FIGS. 10 and 11, over the line parts LP1, and over a part ofthe line part LP2, namely, over a part of the electrode 16, the capinsulation films CP1 is formed in at least a region in contact with theelectrode 23 via the capacitive insulation film 27 in plan view. The capinsulation film CP1 is formed of an insulation film IF3 such as asilicon nitride film.

Incidentally, in a region of the top surface of each line part LP1 inwhich the cap insulation film CP1 is formed, the metal silicide film 33is not formed. On the other hand, at the region of the top surface ofthe line part LP2 in the vicinity of each plug PG1, and at the topsurface of the dummy electrode DE, the metal silicide films 33 areformed, but the cap insulation film CP1 is not formed.

Also in the present third modified example, as with First Embodiment,each plug PG2 can be electrically coupled with any portion of theelectrode 23 at a low resistance. This can prevent an electric shortcircuit between the electrode 16 and the electrode 23 through the plugPG2. Thus, the capacity of the capacitive element can be increased withease, and the contact hole CH2 can be aligned with ease.

On the other hand, in the present third modified example, the region ofthe electrode 16 in contact with the electrode 23 via the capacitiveinsulation film 27 in plan view is covered with the cap insulation filmCP1. Therefore, in the present third modified example, as compared withFirst Embodiment, it is possible to prevent the adjacent electrode 16and electrode 23 from being electrically short-circuited with morereliability.

<Configuration of Memory Cell>

When, a description will be given to the memory cell of the flash memory4 (see FIG. 1) formed in the semiconductor chip CHP (see FIG. 1), thecapacitive element for use in the analog circuit (see FIG. 1) or thedriving circuit of the flash memory 4 by reference to the accompanyingdrawings.

FIGS. 12 and 13 are each a cross sectional view showing thesemiconductor device of First Embodiment. FIG. 12 is a cross sectionalview showing the structure of the memory cell of the flash memory, andthe structure of the capacitive element formed in an analog circuit orthe like. FIG. 13 is a cross sectional view showing the periphery of aninsulation film 27 a of the memory cell.

As shown in FIG. 12, the memory cell is formed in a memory cellformation region AR1 of the semiconductor chip, and the capacitiveelement is formed in a capacitive element formation region AR2 of thesemiconductor chip. Namely, the semiconductor device has the memory cellformed in the memory cell formation region AR1, and the capacitiveelement formed in the capacitive element formation region AR2.

First, a description will be given to the structure of the memory cellof the flash memory. The semiconductor device has a p type well 12, agate insulation film 13, a control gate electrode 15, a memory gateelectrode 26, an insulation film 27 a as a gate insulation film, and lowdensity impurity diffusion regions 28 and high density impuritydiffusion regions 30 as a source region and a drain region. The gateinsulation film 13, the control gate electrode 15, the insulation film27 a, and the memory gate electrode 26 form the memory cell.

As shown in FIG. 12, in the memory cell formation region AR1, a p typewell 12 is formed in the semiconductor substrate 10. Over the p typewell 12, there is formed the memory cell. The memory cell is formed of aselection part for selecting a memory cell, and a storage part forstoring information.

First, a description will be given to the configuration of the selectionpart for selecting a memory cell. The memory cell has a gate insulationfilm 13 formed over a semiconductor substrate 10, namely, a p type well12. Over the gate insulation film 13, there is formed the control gateelectrode 15. The gate insulation film 13 is formed of an insulationfilm IF1 at the same layer as the insulation film IF1 between electrode16 and the semiconductor substrate 10, such as a silicon oxide film. Thecontrol gate electrode 15 is formed of a conductive film CF1 such as apolysilicon film, and a metal silicide film 33 such as a cobalt silicidefilm formed at the surface of the conductive film CF1. Namely, thecontrol gate electrode 15 is formed of a conductive film CF1 at the samelayer as the conductive film CF1 forming the electrode 16. The metalsilicide film 33 is formed for reducing the resistance of the controlgate electrode 15. The control gate electrode 15 has a function ofselecting a memory cell. In other words, a specific memory cell isselected by the control gate electrode 15. Thus, a write operation, anerase operation, or a read operation is executed on the selected memorycell.

Then, a description will be given to the configuration of the memorycell. At one side surface of the control gate electrode 15, there isformed a memory gate electrode 26 via the insulation film 27 a. Thememory gate electrode 26 is formed in a sidewall shape formed at oneside surface of the control gate electrode 15, and is formed of aconductive film CF2 such as a polysilicon film, and a metal silicidefilm 33 such as a cobalt silicide film formed at the surface of theconductive film CF2. Namely, the memory gate electrode 26 is formed ofthe conductive film CF2 at the same layer as the conductive film CF2forming the electrode 23. The metal silicide film 33 is formed forreducing the resistance of the memory gate electrode 26.

Between the control gate electrode 15 and the memory gate electrode 26,and between the memory gate electrode 26 and the semiconductor substrate10, there is formed an insulation film 27 a as the gate insulation film.The insulation film 27 a is formed of the insulation film IF2 at thesame layer as the insulation film IF2 forming the capacitive insulationfilm 27. As shown in FIG. 13, the insulation film IF2 forming theinsulation film 27 a is formed of a silicon oxide film 17 formed overthe semiconductor substrate 10, a charge accumulation film 25 (siliconnitride film 18) formed over the silicon oxide film 17, and a siliconoxide film 19 formed over the charge accumulation film 25. The siliconoxide film 17 functions as a gate insulation film formed between thememory gate electrode 26 and the semiconductor substrate 10. The gateinsulation film formed of the silicon oxide film 17 also has a functionas a tunnel insulation film. For example, the storage part of the memorycell injects electrons into the charge accumulation film 25, or injectsholes into the charge accumulation film 25 from the semiconductorsubstrate 10 via the silicon oxide film 17, and thereby performs storageor erase of information. Accordingly, the silicon oxide film 17functions as a tunnel insulation film.

Then, the charge accumulation film 25 formed over the silicon oxide film17 has a function of accumulating electric charges. Specifically, in thepresent First Embodiment, the charge accumulation film 25 is formed ofthe silicon nitride film 18. The storage part of the memory cell in thepresent First Embodiment controls the current flowing in thesemiconductor substrate 10, namely, in the p type well 12 under thememory gate electrode 26 by the presence or absence of electric chargesaccumulated in the charge accumulation film 25, and thereby storesinformation. In other words, information is stored by utilizing thefollowing: the threshold voltage of the current flowing in thesemiconductor substrate 10 under the memory gate electrode 26 changes bythe presence or absence of electric charges accumulated in the chargeaccumulation film 25.

In the present First Embodiment, an insulation film having a trap levelis used as the charge accumulation film 25. As one example of theinsulation film having a trap level, mention may be made of the siliconnitride film 18. However, not limited to the silicon nitride film, theremaybe used, for example, an aluminum oxide film (alumina). When theinsulation film having a trap level is used as the charge accumulationfilm 25, electric charges are trapped at the trap level formed in theinsulation film. By thus trapping electric charges at the trap level,electric charges are accumulated in the insulation film.

At one sidewall, namely, one side surface of both sidewalls of thecontrol gate electrode 15, there is formed the memory gate electrode 26.Whereas, at the other sidewall, namely, the other side surface thereof,there is formed a sidewall 29 a formed of a silicon oxide film.Similarly, at one sidewall, namely, one side surface of both sidewallsof the memory gate electrode 26, there is formed the control gateelectrode 15. Whereas, at the other sidewall, namely, the other sidesurface thereof, there is formed a sidewall 29 a formed of a siliconoxide film.

In the semiconductor substrate 10 immediately under the sidewall 29 a,there are formed a pair of shallow low density impurity diffusionregions 28 which are n type semiconductor regions. In outer regions incontact with the pair of shallow low density impurity diffusion regions28, there are formed a pair of deep high density impurity diffusionregions 30, respectively. The deep high density impurity diffusionregions 30 are also n type semiconductor regions. At the surface of eachhigh density impurity diffusion region 30, there is formed the metalsilicide film 33 formed of, for example, a cobalt silicide film. Thepair of low density impurity diffusion regions 28 and the pair of highdensity impurity diffusion regions 30 form the source region or thedrain region of the memory cell. The source region and the drain regionare formed of the low density impurity diffusion region 28 and the highdensity impurity diffusion region 30. As a result, the source region andthe drain region can be formed in a LDD (Lightly Doped Drain) structure.

Incidentally, for the source region and the drain region, one is formedin alignment with the control gate electrode 15, and the other is formedin alignment with the memory gate electrode 26.

Herein, the transistor formed of the gate insulation film 13, thecontrol gate electrode 15, and the source region and the drain region isassumed to be referred to as a selection transistor. On the other hand,the transistor formed of the insulation film 27 a, the memory gateelectrode 26, and the source region and the drain region is assumed tobe referred to as a memory transistor. As a result, it can be said thatthe selection part of the memory cell is formed of a selectiontransistor, and that the storage part of the memory cell is formed of amemory transistor. The memory cell is formed in this manner.

Then, a description will be given to the wiring structure to be coupledwith the memory cell. Over the memory cell, an interlayer insulationfilm 34 formed of a silicon oxide film is formed in such a manner as tocover the memory cell. In the interlayer insulation film 34, there isformed each contact hole CH4 penetrating through the interlayerinsulation film 34, and reaching the metal silicide film 33 formed atthe surface of the high density impurity diffusion region 30 forming thesource region or the drain region. In the inside of the contact holeCH4, there is embedded a conductive film. As the conductive film, first,there is formed a titanium/titanium nitride film which is a barrierconductive film. Then, a tungsten film is formed in such a manner as tofill the contact hole CH4. Thus, the titanium/titanium nitride film anda tungsten film are embedded in the contact hole CH4. This results inthe formation of a plug PG4 formed of a conductive film embedded in thecontact hole CH4, and electrically coupled with the source region or thedrain region. Then, over the interlayer insulation film 34, there isformed a wire HL4. The wire HL4 and the plug PG4 are electricallycoupled with each other. The wire HL4 is formed of a lamination film of,for example, a titanium/titanium nitride film, an aluminum film, and atitanium/titanium nitride film.

Incidentally, the plugs PG1, PG2, and PG3 are also formed in the samemanner as with the plug PG4. The wires HL1, HL2, and HL3 are also formedin the same manner as with the wire HL4.

The memory cell in the present First Embodiment is configured asdescribed above. Below, a description will be given to the operation ofthe memory cell. Herein, the voltage to be applied to the control gateelectrode 15 is referred to as Vcg, and the voltage to be applied to thememory gate electrode 26 is referred to as Vmg. Further, the respectivevoltages to be applied to the source region and the drain region arereferred to as Vs and Vd, respectively. The voltage to be applied to thesemiconductor substrate 10, namely, the p type well 12 is referred to asVb. The injection of electrons into the silicon nitride film 18 which isthe charge accumulation film 25 is defined as “write”. The injection ofholes into the silicon nitride film 18 is defined as “erase”.

First, the write operation will be described. The write operation isperformed by hot electron write referred to as so-called source sideinjection method. As the write voltage, for example, the voltage Vs tobe applied to the source region is set at 6 V; the voltage Vmg to beapplied to the memory gate electrode 26 is set at 12 V; and the voltageVcg to be applied to the control gate electrode 15 is set at 1.5 V.Then, the voltage Vd to be applied to the drain region is controlled sothat the channel current for write becomes a given set value. Thevoltage Vd at this step is determined by the set value of the channelcurrent and the threshold voltage of the selection transistor having thecontrol gate electrode 15, and becomes, for example, about 1 V. Thevoltage Vb to be applied to the p type well 12, namely, thesemiconductor substrate 10 is 0 V.

A description will be given to the movement of electric charges whensuch a voltage is applied to perform the write operation. As describedabove, a potential difference is caused between the voltage Vs to beapplied to the source region and the voltage Vd to be applied to thedrain region. As a result, electrons flow in the channel region formedbetween the source region and the drain region. The electrons flowing inthe channel region are accelerated in the channel region under thevicinity of the border between the control gate electrode 15 and thememory gate electrode 26, and become hot electrons. Then, under theelectric field by the positive voltage (Vmg=12V) applied to the memorygate electrode 26, hot electrons are injected into the chargeaccumulation film 25, namely, the silicon nitride film 18 under thememory gate electrode 26. The injected hot electrons are trapped at thetrap level in the silicon nitride film 18. As a result, electrons areaccumulated in the silicon nitride film 18, resulting in an increase inthreshold voltage of the memory transistor. The write operation isperformed in this manner.

Subsequently, the erase operation will be described. The erase operationis performed by, for example, BTBT (Band to Band Tunneling) erase usingan inter-band tunneling phenomenon. With BTBT erase, for example, thevoltage Vmg to be applied to the memory gate electrode 26 is set at −6V; the voltage Vs to be applied to the source region is set at 6 V; andthe voltage Vcg to be applied to the control gate electrode 15 is set at0 V; and the drain region is applied with 0 V. As a result, the holesgenerated by the inter-band tunneling phenomenon at the surface regionend by the voltage caused across the source region and the memory gateelectrode are accelerated by the high voltage applied to the sourceregion, and become hot holes. Then, some of the hot holes are attractedto the negative voltage applied to the memory gate electrode 26, and areinjected into the silicon nitride film 18. The injected hot holes aretrapped at the trap level in the silicon nitride film 18, resulting inthe reduction of the threshold voltage of the memory transistor. Theerase operation is performed in this manner.

Then, the read operation will be described. Read is performed in thefollowing manner: the voltage Vd to be applied to the drain region isset at Vdd (1.5 V), the voltage Vs to be applied to the source region isset at 0 V, the voltage Vcg to be applied to the control gate electrode15 is set at Vdd (1.5 V), and the voltage Vmg to be applied to thememory gate electrode 26 is set at Vdd (1.5 V); thus, a current ispassed in the opposite direction to that for write. The following isalso acceptable: the voltage Vd to be applied to the drain region andthe voltage Vs to be applied to the source region are interchanged, andare set at 0 V and 1.5 V, respectively; thus, read is performed with thecurrent in the same direction as that for write. At this step, when thememory cell in the write state, and the threshold voltage is high, acurrent does not flow through the memory cell. On the other hand, whenthe memory cell is in the erase state, and the threshold voltage is low,a current flows through the memory cell.

<Method for Manufacturing a Semiconductor Device>

Then, a description will be given to a method for manufacturing asemiconductor device of the present First Embodiment.

FIGS. 14 to 31 are each a cross sectional view of the semiconductordevice during a manufacturing step in First Embodiment. FIGS. 14 to 31each show the same cross section as the cross section shown in FIG. 12.

First, as shown in FIG. 14, there is provided a semiconductor substrate10 formed of a silicon single crystal doped with p type impurities suchas boron (B). Then, in the semiconductor substrate 10, there is formedan element isolation region 11 for isolating, for example, a lowbreakdown voltage MISFET formation region and a high breakdown voltageMISFET formation region from each other. The element isolation region 11is provided in order to prevent elements from interfering with oneanother. The element isolation region 11 can be formed using, forexample, a LOCOS (Local Oxidation of Silicon) method or a STI (ShallowTrench Isolation) method.

For example, with the STI method, the element isolation region 11 isformed in the following manner. Namely, in the semiconductor substrate10, an element isolation trench is formed using a photolithographytechnology and an etching technology. Then, a silicon oxide film isformed over the semiconductor substrate 10 in such a manner as to fillthe element isolation trench. Then, by a Chemical Mechanical Polishing:CMP) method, unnecessary portions of the silicon oxide film formed overthe semiconductor substrate 10 are removed. As a result, there can beformed the element isolation region 11 in which the silicon oxide filmis embedded only in the element isolation trench. Incidentally, FIG. 14shows the region of the memory cell formation region AR1 on the frontsurface 10 a side of the semiconductor substrate 10 in which the elementisolation region 11 is not formed, and the region of the capacitiveelement formation region AR2 on the front surface 10 a side of thesemiconductor substrate 10 in which the element isolation region 11 isformed.

Then, the semiconductor substrate 10 is doped with impurities to form ap type well 12. The p type well 12 is formed by doping p type impuritiessuch as boron into the semiconductor substrate 10 with the ionimplantation method. Then, in the memory cell formation region AR1, asemiconductor region (not shown) for forming the channel of theselection transistor is formed in the surface region of the p type well12. The semiconductor region for channel formation is formed foradjusting the threshold voltage forming the channel.

Then, as shown in FIG. 15, in the memory cell formation region AR1 andthe capacitive element formation region AR2, an insulation film IF1 isformed over the semiconductor substrate 10. The insulation film IF1 isformed of, for example, a silicon oxide film, and can be formed using,for example, a thermal oxidation method. However, the insulation filmIF1 is not limited to a silicon oxide film, and may be variouslychanged. For example, the insulation film IF1 may be a siliconoxynitride film (SIGN). Namely, nitrogen may be segregated at theinterface between the insulation film IF1 and the semiconductorsubstrate 10. The silicon oxynitride film is higher than the siliconoxide film in terms of the effects of suppressing the generation of theinterface state in the film, and reducing electron trap. Therefore, thehot carrier resistance of the insulation film IF1 can be improved, andthe insulation resistance can be improved. Further, the Siliconoxynitride film is less susceptible to diffusion of impurities thereinas compared with the silicon oxide film. For this reason, by using asilicon oxynitride film for the gate insulation film 13, it is possibleto suppress variations in threshold voltage caused by diffusion ofimpurities in the control gate electrode 15 toward the semiconductorsubstrate 10 side. For the formation of a silicon oxynitride film, forexample, the semiconductor substrate 10 may be desirably heat-treated inan atmosphere containing nitrogen such as NO, NO₂, or NH₃.Alternatively, the same effects can also be obtained in the followingmanner: an insulation film IF1 formed of a silicon oxide film is formedover the surface of the semiconductor substrate 10; then, thesemiconductor substrate 10 is heat-treated in an atmosphere containingnitrogen; accordingly, nitrogen is segregated at the interface betweenthe insulation film IF1 and the semiconductor substrate 10.

Alternatively, the insulation film IF1 may be formed of, for example, ahigh dielectric constant film having a higher dielectric constant thanthat of a silicon nitride film. As a result, even with the samecapacity, the physical film thickness can be increased. For this reason,the leakage current can be reduced.

For example, as a high dielectric constant film, there is used a hafniumoxide (HfO₂) film which is one of hafnium oxides. However, in place ofthe hafnium oxide film, there can also be used other hafnium typeinsulation films such as a hafnium aluminate (HfAlO) film, a hafniumoxynitride (HfON) film, a hafnium silicate (HfSiO) film, and a hafniumsilicon oxynitride (HfSiON) film. Further, there can also be usedhafnium type insulation films obtained by doping the hafnium typeinsulation films with oxides such as tantalum oxide, niobium oxide,titanium oxide, zirconium oxide, lanthanum oxide, and yttrium oxide. Thehafnium type insulation films are, as with a hafnium oxide film, higherin dielectric constant than a silicon oxide film and a siliconoxynitride film, and hence can provide the same effects as those when ahafnium oxide film is used.

Then, in the memory cell formation region AR1 and the capacitive elementformation region AR2, a conductive film CF1 formed of a polysilicon filmis formed over the insulation film IF1. The conductive film CF1 formedof a polysilicon film can be formed using, for example, a CVD (ChemicalVapor Deposition) method. Then, using a photolithography technology andan ion implantation method, n type impurities such as phosphorus orarsenic are doped into the conductive film CF1 formed of a polysiliconfilm.

Then, as shown in FIG. 16, in the memory cell formation region AR1 andthe capacitive element formation region AR2, the conductive film CF1 andthe insulation film IF1 are processed, namely, patterned by etchingusing a patterned resist film as a mask. Then, in the memory cellformation region AR1, there are formed a control gate electrode 15formed of the conductive film CF1, and a gate insulation film 13 formedof the insulation film IF1 between the control gate electrode 15 and thesemiconductor substrate 10. Whereas, in the capacitive element formationregion AR2, there are formed an electrode 16 formed of the conductivefilm CF1, and a dummy electrode DE formed of the conductive film CF1.The control gate electrode 15 is the gate electrode of the selectiontransistor of the memory cell. Thus, the electrode 16 and the dummyelectrode DE of the capacitive element are formed in the step of formingthe control gate electrode 15 of the memory cell.

Herein, in the control gate electrode 15, n type impurities are dopedinto the conductive film CF1 formed of a polysilicon film. For thisreason, the work function value of the control gate electrode 15 can beset at a value in the vicinity of the conduction band of silicon (4.15eV). For this reason, it is possible to reduce the threshold voltage ofthe selection transistor which is an n channel type MISFET.

Herein, when a semiconductor device of a third modified example of FirstEmbodiment is manufactured, the following steps described by referenceto FIGS. 17 to 19 can be performed as a modified example in place of thestep described by reference FIG. 16.

First, after the step described by reference to FIG. 15, as shown inFIG. 17, an insulation film IF3 is formed over the conductive film CF1formed of a polysilicon film. The insulation film IF3 formed of asilicon nitride film can be formed using, for example, a CVD method.Incidentally, for the materials for the insulation film IF3, insulationfilms formed of other materials functioning as a cap insulation film, ahard mask film, or a spacer film can be used in place of the siliconnitride film.

Then, as shown in FIG. 18, by etching using a patterned resist film as amask, the insulation film IF3 is processed. Thus, in the region of thecapacitive element formation region AR2 in which a metal silicide filmis formed, the insulation film IF3 is removed. In the region of thecapacitive element formation region AR2 except for the region in which ametal silicide film is formed, the insulation film IF3 is left.Incidentally, as shown in FIG. 18, in the memory cell formation regionAR1, the insulation film IF3 can be left.

Then, as shown in FIG. 19, by etching using a patterned resist film as amask, the insulation film IF3, the conductive film CF1, and theinsulation film IF1 are processed. As a result, in the memory cellformation region AR1, there are formed the gate insulation film 13, thecontrol gate electrode 15, and the cap insulation film CP1 formed of theinsulation film IF3 over the control gate electrode 15. Whereas, in thecapacitive element formation region AR2, the electrode 16 is formed.Over a part of the top surface of the electrode 16, there is formed thecap insulation film CP1 formed of the insulation film IF3. Incidentally,after performing the step shown in FIG. 19, the same steps as the stepshown in FIG. 20 and later steps can be performed in the same manner asafter performing the step shown in FIG. 16.

Then, as shown in FIG. 20, in the memory cell formation region AR1 andthe capacitive element formation region AR2, an insulation film IF2 isformed over the semiconductor substrate 10 including the surface of thecontrol gate electrode 15, the surface of the electrode 16, and thesurface of the dummy electrode DE. In FIG. 20, the insulation film IF2is shown as a one-layer film. However, as shown on an enlarged scale inFIG. 21, the insulation film IF2 is formed of, for example, a siliconoxide film 17, a silicon nitride film 18 over the silicon oxide film 17,and a silicon oxide film 19 formed over the silicon nitride film 18, andis a so-called ONO film. The insulation film IF2 can be formed using,for example, a CVD method. Then, for example, the film thickness of thesilicon oxide film 17 is 5 nm. The film thickness of the silicon nitridefilm 18 is 10 nm. The film thickness of the silicon oxide film 19 is 5nm.

The silicon nitride film 18 of the insulation film IF2 is a film to bethe charge accumulation film 25 of the memory transistor (see FIG. 13)in the memory cell formation region AR1. In the present FirstEmbodiment, as the charge accumulation film 25, there is used thesilicon nitride film 18. However, as the charge accumulation films 25,there may be used other insulation films having a trap level. Forexample, an aluminum oxide film (alumina film) can also be used as thecharge accumulation film 25.

Then, as shown in FIG. 20, in the memory cell formation region AR1 andthe capacitive element formation region AR2, the conductive film CF2formed of, for example, a polysilicon film is formed over the insulationfilm IF2. The conductive film CF2 formed of a polysilicon film can beformed using, for example, a CVD method.

Then, as shown in FIG. 22, in the memory cell formation region AR1 andthe capacitive element formation region AR2, the conductive film CF2formed of, for example, a polysilicon film is etched back by anisotropicetching. As a result, in the memory cell formation region AR1, asidewall 22 a and a sidewall 22 b each formed of the conductive film CF2are left at the sidewalls, namely, the side surfaces on the oppositesides of the control gate electrode 15 via the insulation film IF2. Onthe other hand, in the capacitive element formation region AR2, theconductive film CF2 is integrally left between the electrode 16 and thedummy electrode DE, at the circumferential side surface of the electrode16, and at the circumferential side surface of the dummy electrode DEvia the insulation film IF2. Thus, the electrode 23 formed of the leftconductive film CF2 is integrally formed. For this reason, the electrode16 and the electrode 23 do not overlap with each other in plan view.

Herein, when the semiconductor device in the second modified example ofFirst Embodiment is manufactured, after performing the step described byreference to FIG. 20, the following steps described by reference toFIGS. 23 and 24 can be performed in place of the step described byreference to FIG. 22.

First, as shown in FIG. 23, after applying a resist film PR1 onto thesemiconductor substrate 10, the resist film PR1 is subjected to anexposure/development treatment, thereby to be patterned. The patterningis performed so as to achieve the following: in the capacitive elementformation region AR2, in the top surface of the electrode 16, in aregion in which the electrode 23 is formed, the conductive film CF2 iscovered with the resist film PR1; and in other regions, the conductivefilm CF2 is exposed.

Then, as shown in FIG. 24, the conductive film CF2 formed of apolysilicon film is etched back by anisotropic etching. As a result, inthe memory cell formation region AR1, at the sidewalls, namely, the sidesurfaces on the opposite sides of the control gate electrode 15, thereare left a sidewall 22 a and a sidewall 22 b each formed of theconductive film CF2. On the other hand, in the capacitive elementformation region AR2, the conductive film CF2 formed of, for example, apolysilicon film is anisotropically etched. As a result, between theelectrode 16 and the dummy electrode DE, at the circumferential sidesurface of the electrode 16, and at the circumferential side surface ofthe dummy electrode DE, there is formed the electrode 23 formed of theintegrally formed conductive film CF2. Whereas, in the capacitiveelement formation region AR2, using a resist film PR1 as a mask, theconductive film CF2 formed of a polysilicon film is etched. As a result,in a partial region of the top surface of the electrode 16, there isformed the electrode 23 via the insulation film IF2. At this step, in apartial region of the top surface of the electrode 16, the electrode 16and the electrode 23 overlap each other in plan view. Then, thepatterned resist film PR1 is removed. Incidentally, after performing thestep shown in FIG. 24, the same steps as the step shown in FIG. 25 andlater steps can be performed in the same manner as after performing thestep shown in FIG. 22.

Then, as shown in FIG. 25, after applying a resist film PR2 onto thesemiconductor substrate 10, the resist film PR2 is subjected to anexposure/development treatment. As a result, the resist film PR2 ispatterned. The patterning is performed so as to achieve the following:while the capacitive element formation region AR2 is fully covered, thememory cell formation region AR1 is partially opened. Specifically, thepatterning is performed so as to expose the sidewall 22 b formed at thesidewall, namely, the side surface on one side of the control gateelectrode 15 in the memory cell formation region AR1. For example, inFIG. 25, there is exposed the sidewall 22 b formed at the sidewall onthe left hand side of the control gate electrode 15.

Then, as shown in FIG. 26, by etching using the patterned resist filmPR2 as a mask, the sidewall 22 b exposed at the sidewall on the lefthand side of the control gate electrode 15 is removed. At this step, thesidewall 22 a formed at the sidewall on the right hand side of thecontrol gate electrode 15 is covered with the resist film PR2, and henceis left without being removed. The sidewall 22 a is a portion to be amemory gate electrode 26 (see FIG. 27 described later). Further, also inthe capacitive element formation region AR2, the electrode 23 isprotected by the resist film PR2, and hence is left without beingremoved. Then, the patterned resist film PR2 is removed.

Subsequently, as shown in FIG. 27, in the memory cell formation regionAR1 and the capacitive element formation region AR2, the exposedportions of the insulation film IF2, namely, the portions of theinsulation film IF2 not covered with any of the electrode 23, and thesidewall 22 a to be the memory gate electrode 26 are etched, and therebyremoved. Namely, in the memory cell formation region AR1, the portionsof the insulation film IF2 between the control gate electrode 15 and thememory gate electrode 26, and between the memory gate electrode 26 andthe semiconductor substrate 10 are left, and other portions thereof areremoved. Whereas, in the capacitive element formation region AR2, theportions of the insulation film IF2 between the electrode 16 and theelectrode 23, between the dummy electrode DE and the electrode 23, andbetween the electrode 23 and the semiconductor substrate 10 are left,and other portions thereof are removed.

Thus, in the memory cell formation region AR1, only at the sidewall,namely, the side surface on the right hand side of the control gateelectrode 15, there is left the sidewall 22 a formed of the conductivefilm CF2 via the insulation film IF2, resulting in the formation of thesidewall-shaped memory gate electrode 26. Whereas, the portion betweenthe control gate electrode 15 and the memory gate electrode 26, and theportion between the memory gate electrode 26 and the semiconductorsubstrate 10 of the insulation film IF2 are left. The left insulationfilm IF2 becomes an insulation film 27 a. At this step, in theinsulation film 27 a, the silicon nitride film 18 forming the insulationfilm 27 a (see FIG. 21) becomes the charge accumulation film 25 (seeFIG. 13).

On the other hand, in the capacitive element formation region AR2, theportion between the electrode 16 and the electrode 23, the portionbetween the dummy electrode DE and the electrode 23, and the portionbetween the electrode 23 and the semiconductor substrate 10 of theinsulation film IF2 are left. The left insulation film IF2 becomes acapacitive insulation film 27. The capacitive insulation film 27 isformed of the silicon oxide film 17, the silicon nitride film 18, andthe silicon oxide film 19 (see FIG. 21). Then, the electrode 16, theelectrode 23, and the capacitive insulation film 27 form a capacitiveelement.

Incidentally, at this point in time, the conductive film CF1 is formedof a polysilicon film. Accordingly, the memory gate electrode 26 of thememory cell and the electrode 23 of the capacitive element are eachformed of a polysilicon film.

Then, as shown in FIG. 28, by using a photolithography technology and anion implantation method, in the memory cell formation region AR1, thereis formed a shallow low density impurity diffusion region 28 inalignment with the control gate electrode 15 and the memory gateelectrode 26. The shallow low density impurity diffusion region 28 is ann type semiconductor region doped with n type impurities such asphosphorus or arsenic.

Subsequently, as shown in FIG. 29, over the semiconductor substrate 10,there is formed an insulation film formed of a silicon oxide film. Theinsulation film formed of a silicon oxide film can be formed using, forexample, a CVD method. Then, the insulation film is anisotropicallyetched, thereby to form sidewalls 29 a and 29 b. In the memory cellformation region AR1, at the sidewall, namely, the side surface on theleft hand side of the control gate electrode 15, and at the sidewall,namely, the side surface on the right hand side of the memory gateelectrode 26, there are formed sidewalls 29 a formed of an insulationfilm. On the other hand, in the capacitive element formation region AR2,at the sidewall, namely, the side surface of the electrode 23, there isformed a sidewall 29 b formed of an insulation film. Each insulationfilm forming the sidewalls 29 a and 29 b was formed of a monolayer filmof a silicon oxide film. However, the insulation film is not limitedthereto, and may be formed of a lamination film of, for example, asilicon nitride film and a silicon oxide film.

Herein, when the semiconductor device in the second modified example ofFirst Embodiment is manufactured, in the step described by reference toFIG. 29, in the capacitive element formation region AR2, at the sidewallof the portion of the electrode 23 formed at the top surface of theelectrode 16, there is formed a sidewall 29 c (see FIG. 8).

Then, as shown in FIG. 30, by using a photolithography technology and anion implantation method, in the memory cell formation region AR1, thereis formed a deep high density impurity diffusion region 30 in alignmentwith the sidewall 29 a. The deep high density impurity diffusion region30 is an n type semiconductor region doped with n type impurities suchas phosphorus or arsenic. The deep high density impurity diffusionregion 30 and the shallow low density impurity diffusion region 28 formthe source region and the drain region of the memory cell. Thus, thesource region and the drain region are each formed of the shallow lowdensity impurity diffusion region 28 and the deep high density impuritydiffusion region 30. As a result, the source region and the drain regioncan be formed in a LDD structure. After thus forming the high densityimpurity diffusion region 30, a heat treatment at about 1000° C. isperformed. As a result, the doped impurities are activated.

Then, as shown in FIG. 31, at the surfaces of the control gate electrode15, the memory gate electrode 26, the electrode 16, the electrode 23,the dummy electrode DE, and the high density impurity diffusion regions30 as the source region and the drain region, there are formed metalsilicide films 33.

First, in the memory cell formation region AR1 and the capacitiveelement formation region AR2, a metal film formed of, for example, acobalt film is formed over the semiconductor substrate 10. At this step,in the memory cell formation region AR1, the metal films are formed insuch a manner as to be in direct contact with the exposed control gateelectrode 15 and memory gate electrode 26. Similarly, the metal film isalso in direct contact with the deep high density impurity diffusionregion 30. On the other hand, in the capacitive element formation regionAR2, the metal films are in direct contact with a part of the electrode16 and a part of the electrode 23. The metal film formed of, forexample, a cobalt film can be formed using, for example, a sputteringmethod. The film thickness of the metal film is, for example, 10 nm.

Then, a first heat treatment is performed on the semiconductor substrate10. Then, the surface of the semiconductor substrate 10 is cleaned. Thecleaning is performed by APM (Ammonium hydroxide hydrogen PeroxideMixture cleaning) cleaning and HPM cleaning. The APM cleaning iscleaning with a mixed chemical including ammonium hydroxide(NH₄OH)/hydrogen peroxide (H₂O₂)/pure water (H₂O), and having a largeeffect of removing particles or organic substances. On the other hand,the HPM cleaning is cleaning with a mixed chemical includinghydrochloric acid (HCl)/hydrogen peroxide (H₂O₂)/pure water (H₂O), andhaving a large effect of removing metals. Subsequently, after cleaning,a second heat treatment is performed.

As a result, as shown in FIG. 31, in the memory cell formation regionAR1, at the surface of the control gate electrode 15, and the surface ofthe memory gate electrode 26, the conductive films CF1 and CF2 formed ofa polysilicon film, and the metal films formed of a cobalt film reactwith each other, resulting in the formation of the metal silicide films33 formed of a cobalt silicide film. As a result, the control gateelectrode 15 is formed in a lamination structure of the conductive filmCF1 formed of a polysilicon film and the metal silicide film 33 formedof a cobalt silicide film. Whereas, the memory gate electrode 26 isformed in a lamination structure of the conductive film CF2 formed of apolysilicon film, and the metal silicide film 33 formed of a cobaltsilicide film. The metal silicide film 33 formed of a cobalt silicidefilm is formed for reducing the resistances of the control gateelectrode 15 and the memory gate electrode 26. Further, the gateinsulation film 13, the control gate electrode 15, the memory gateelectrode 26, and the insulation film 27 a form the memory cell.

Similarly, by the heat treatment, also at the surface of the highdensity impurity diffusion region 30, the high density impuritydiffusion region 30 formed of silicon and the metal film formed of acobalt film react with each other, resulting in the formation of themetal silicide film 33 formed of a cobalt silicide film. For thisreason, also in the high density impurity diffusion region 30, a lowerresistance can be achieved.

On the other hand, in the capacitive element formation region AR2, atthe surface of the electrode 16, the surface of the dummy electrode DE,and the surface of the electrode 23, the conductive films CF1 and CF2formed of a polysilicon film, and the metal films formed of a cobaltfilm react with each other, resulting in the formation of the metalsilicide films 33 formed of a cobalt silicide film. As a result, theelectrode 16 and the dummy electrode DE are each formed in a laminationstructure of the conductive film CF1 formed of a polysilicon film, andthe metal silicide film 33 formed of a cobalt silicide film. Whereas,the electrode 23 is formed in a lamination structure of the conductivefilm CF2 formed of a polysilicon film, and the metal silicide film 33formed of a cobalt silicide film. The metal silicide film 33 formed of acobalt silicide film is formed for reducing the resistances of theelectrode 16, the dummy electrode DE, and the electrode 23.

Then, the unreacted metal film is removed from over the semiconductorsubstrate 10. Incidentally, in the present First Embodiment, adescription has been given to the example in which a cobalt silicidefilm is formed as the metal silicide film 33. However, it is alsoacceptable that, as the metal silicide film 33, for example, a nickelsilicide film or a titanium silicide film is formed in place of thecobalt silicide film.

In the manner described up to this point, in the memory cell formationregion AR1, the memory cell can be formed, and in the capacitive elementformation region AR2, the capacitive element in the present FirstEmbodiment can be formed.

Incidentally, when the semiconductor device in the third modifiedexample of First Embodiment is manufactured, in the step described byreference to FIG. 31, as described previously by reference to FIG. 11,the metal silicide film 33 is not formed in the region of the topsurface of the electrode 16 in which the cap insulation film CP1 isformed.

Then, the wiring step will be described by reference to FIG. 12. Asshown in FIG. 12, over the front surface 10 a of the semiconductorsubstrate 10, there is formed an interlayer insulation film 34. Theinterlayer insulation film 34 is formed of, for example, a silicon oxidefilm, and can be formed using a CVD method using, for example, TEOS(Tetra Ethyl Ortho Silicate) as a raw material. Then, the surface of theinterlayer insulation film 34 is planarized using, for example, a CMPmethod.

Subsequently, using a photolithography technology and an etchingtechnology, contact holes CH1, CH2, and CH4 are formed in the interlayerinsulation film 34. At this step, in the memory cell formation regionAR1, there is formed the contact hole CH4 penetrating through theinterlayer insulation film 34, and reaching the source region or thedrain region. Whereas, in the capacitive element formation region AR2,there are formed contact holes CH1 and CH2. The contact hole CH1penetrates through the interlayer insulation film 34, and reaches theelectrode 16. Further, the contact hole CH2 penetrates through theinterlayer insulation film 34, and reaches the portion of the electrode23 formed at the side surface of the dummy electrode DE opposite to theelectrode 16 side.

Then, over the interlayer insulation film 34 including the bottomsurfaces and the inner walls of the contact holes CH1, CH2, and CH4,there is formed a titanium/titanium nitride film. The titanium/titaniumnitride film is formed of a lamination film of a titanium film and atitanium nitride film, and can be formed using, for example, asputtering method. The titanium/titanium nitride film has a so-calledbarrier property of preventing the diffusion of, for example, tungstenwhich is a material for the film to be embedded in a later step intosilicon.

Subsequently, a tungsten film as a conductive film is formed entirelyover the front surface 10 a of the semiconductor substrate 10 in such amanner as to fill the contact holes CH1, CH2, and CH4. The tungsten filmcan be formed using, for example, a CVD method. Then, the unnecessaryportions of the titanium/titanium nitride film and the tungsten filmformed over the interlayer insulation film 34 are removed by using, forexample, a CMP method. As a result, plugs PG1, PG2, and PG4 can beformed.

Of these, in the capacitive element formation region AR2, the plugs PG1and PG2 are formed. As the plug PG1, there is formed the plug PG1 formedof a conductive film embedded in the contact hole CH1, and electricallycoupled with the electrode 16. As the plug PG2, there is formed the plugPG2 formed of a conductive film embedded in the contact hole CH2, andelectrically coupled with the electrode 23. Incidentally, as the plugPG1, there is formed the plug PG1 in contact with the metal silicidefilm 33 formed over the surface of the electrode 16, and as the plugPG2, there is formed the plug PG2 in contact with the metal silicidefilm 33 formed over the electrode 23.

Then, over the interlayer insulation film 34, and the plugs PG1, PG2,and PG4, there are successively formed, for example, a titanium/titaniumnitride film, an aluminum film containing copper, and atitanium/titanium nitride film. The films can be formed using, forexample, a sputtering method. Subsequently, by using a photolithographytechnology and an etching technology, the films are patterned, therebyto form wires HL1, HL2, and HL4. The wire HL1 is electrically coupledwith the plug PG1; the wire HL2 is electrically coupled with the plugPG2; and the wire HL4 is electrically coupled with the plug PG4.Further, at the overlying layer of the wire, a wire is formed. However,description herein is omitted. Thus, finally, the semiconductor devicein the present First Embodiment can be formed.

<Regarding Coupling between Electrode and Plug>

Semiconductor devices of Comparative Example 1 and Comparative Example 2will be described by reference to the accompanying drawings. FIG. 32 isa cross sectional view showing the semiconductor device of ComparativeExample 1. FIG. 33 is a cross sectional view showing the semiconductordevice of Comparative Example 2. FIGS. 32 and 33 are each a crosssectional view showing the structure of the memory cell of the flashmemory, and the structure of the capacitive element formed in an analogcircuit or the like.

In the semiconductor device of Comparative Example 1, respectiveportions in the memory cell formation region AR1, and respectiveportions other than a lower electrode 116, an upper electrode 123, acontact hole CH102 and a plug PG102 in the capacitive element formationregion AR2 are the same as respective portions of the semiconductordevice of First Embodiment. Whereas, in the semiconductor device ofComparative Example 2, respective portions in the memory cell formationregion AR1, and respective portions other than the lower electrode 116,the upper electrode 123, the contact hole CH102, and the plug PG102 inthe capacitive element formation region AR2 are the same as respectiveportions of the semiconductor device of First Embodiment.

In the semiconductor device of Comparative Example 1, although notshown, in plan view, the lower electrode 116 and the upper electrode 123have different rectangular shapes, and have an overlapping region inwhich the lower electrode 116 and the upper electrode 123 overlap eachother in plan view, and a non-overlapping region in which the lowerelectrode 116 and the upper electrode 123 do not overlap each other inplan view. Namely, in the X axis direction of FIG. 32, the length of thelower electrode 116 is shorter than the length of the upper electrode123. In the Y axis direction crossing with the X axis direction (thedirection perpendicular to the paper plane of FIG. 32), the length ofthe lower electrode 116 is longer than the length of the upper electrode123. In the thus configured overlapping region in which the lowerelectrode 116 and the upper electrode 123 overlap each other in planview, a capacitive element is formed. Then, in the non-overlappingregion of the lower electrode 116, there is formed a plug (not shown)electrically coupled with the lower electrode 116. Whereas, in thenon-overlapping region of the upper electrode 123, there is formed acontact hole CH102 penetrating through the interlayer insulation film34, and reaching the upper electrode 123, and there is formed a plugPG102 formed of a conductive film embedded in the contact hole CH102,and electrically coupled with the upper electrode 123.

As shown in FIG. 32, the lower electrode 116 is formed of a conductivefilm CF1 formed of a polysilicon film and a metal silicide film 33formed over the surface of the conductive film CF1. On the other hand,at the sidewall of the step region of the upper electrode 123, there isformed a sidewall 129 formed of an insulation film. Over the surface ofthe step region of the upper electrode 123, the metal silicide film 33is not formed. For this reason, the upper electrode 123 in the stepregion has a high resistance. Thus, the plug PG102 formed in thenon-overlapping region of the upper electrode 123 cannot be electricallycoupled with the overlapping region of the upper electrode 123 at a lowresistance. Accordingly, the plug PG102 and the upper electrode 123cannot be electrically coupled with each other at a low resistance.

On the other hand, in the semiconductor device of Comparative Example 2,in plan view, the lower electrode 116 and the upper electrode 123 havedifferent rectangular shapes. However, in plan view, the upper electrode123 is formed in such a manner as to be included in the region in whichthe lower electrode 116 is formed. The upper electrode 123 overlaps thelower electrode 116 throughout the entire surface in plan view. For thisreason, in the semiconductor device of Comparative Example 2, the lowerelectrode 116 has an overlapping region in which the lower electrode 116and the upper electrode 123 overlap each other in plan view, and anon-overlapping region in which the lower electrode 116 and the upperelectrode 123 do not overlap each other in plan view. Then, the plug(not shown) electrically coupled with the lower electrode 116 is formedin the non-overlapping region of the lower electrode 116. Whereas, theplug PG102 to be electrically coupled with the upper electrode 123 isformed in the overlapping region of the lower electrode 116. Further, ametal silicide film 33 is formed entirely over the surface of the upperelectrode 123. Accordingly, the plug PG102 and the upper electrode 123can be electrically coupled with each other at a low resistance.

However, in the semiconductor device of Comparative Example 2, thethickness of the capacitive element becomes the total of the thicknessof the lower electrode 116, the thickness of the capacitive insulationfilm 27, and the thickness of the upper electrode 123. Whereas, thethickness of the conductive film CF1 forming the lower electrode 116 isequal to the thickness of the conductive film CF1 forming the controlgate electrode 15. For this reason, the height position of the topsurface of the upper electrode 123 of the capacitive element is higherthan, for example, the height position of the top surface of the controlgate electrode 15 in the memory cell, and is higher than the heightposition of the top surface of the source region or the drain region inthe memory cell. Namely, the distance DST1 in the thickness directionbetween the bottom surface of the wire HL2 over the capacitive elementand the top surface of the upper electrode 123 of the capacitive elementis shorter than the distance DST2 in the thickness direction between thebottom surface of the wire HL4 over the memory cell and the top surfaceof the control gate electrode 15, and is shorter than the distance DST3in the thickness direction between the bottom surface of the wire HL4and the top surface of the source region or the drain region.

Therefore, when the contact hole CH4 penetrating through the interlayerinsulation film 34, and reaching the source region or the drain region,and the contact hole CH102 penetrating through the interlayer insulationfilm 34, and reaching the top surface of the upper electrode 123 areformed in the same step, the contact hole CH102 may penetrate throughthe upper electrode 123 and the capacitive insulation film 27 to reachthe lower electrode 116. In such a case, the plug PG102 formed of aconductive film embedded in the contact hole CH102 may cause a shortcircuit between the upper electrode 123 and the lower electrode 116,resulting in the reduction of the performance of the semiconductordevice.

Further, when the height between the top surface of the semiconductorsubstrate 10 and the bottom surface of the wire HL2 or HL4 is reducedwith miniaturization of a semiconductor device, the ratio of reductionof the distance in the thickness direction between the bottom surface ofthe wire HL2 and the top surface of the upper electrode 123 is largerthan the ratio of reduction of the distance in the thickness directionbetween the bottom surface of the wire HL4 and the top surface of thesource region or the drain region. This results in a still largerpossibility that the plug PG102 formed of a conductive film embedded inthe contact hole CH102 causes a short circuit between the upperelectrode 123 and the lower electrode 116. Accordingly, the performanceof the semiconductor device is further reduced.

<Main Feature and Effect of the Present Embodiment>

On the other hand, in the present First Embodiment, the contact hole CH2penetrates through the interlayer insulation film. 34, and reaches theportion of the electrode 23 formed at the side surface of the dummyelectrode DE opposite to the electrode 16 side. Further, in the presentFirst Embodiment, the plug PG2 formed of a conductive film embedded inthe contact hole CH2 penetrates through the interlayer insulation film34, and is electrically directly coupled with the portion of theelectrode 23 formed at the side surface of the dummy electrode DEopposite to the electrode 16 side. At the portion of the electrode 23 onthe side of the dummy electrode DE opposite to the electrode 16 side,there is formed the electrode 23 as the sidewall with the dummyelectrode DE as the core part. With such a configuration, the plug PG2can be electrically coupled with any portion of the electrode 23 via themetal silicide film 33 formed at the surface of the electrode 23, andhaving a relatively smaller electric resistance. For this reason, theplug PG2 can be electrically coupled with any portion of the electrode23 at a low resistance.

Whereas, in the present First Embodiment, the portion of the electrode23 formed at the side surface of the dummy electrode DE opposite to theelectrode 16 side does not overlap the electrode 16 in plan view.Therefore, the contact hole CH2 does not penetrate through theinterlayer insulation film 34, the electrode 23, and the capacitiveinsulation film 27 to reach the electrode 16. Thus, the plug PG2 formedof a conductive film embedded in the contact hole CH2 does not cause ashort circuit between the electrode 23 and the electrode 16.Accordingly, the performance of the semiconductor device can beimproved.

Incidentally, as shown in FIG. 8, in the second modified example ofFirst Embodiment, at the side surface of the portion of the electrode 23formed over the top surface of the electrode 16, there is formed asidewall 29 c formed of an insulation film. However, as compared withthe height of the side surface at which a sidewall 129 formed of aninsulation film is formed in the step region of the upper electrode 123in Comparative Example 1 as shown in FIG. 32, the height of the sidesurface at which the sidewall 29 c is formed in the second modifiedexample of First Embodiment is smaller. For this reason, as comparedwith the case where the plug PG102 and the upper electrode 123 cannot beelectrically coupled with each other at a low resistance, in the secondmodified example of First Embodiment, the plug PG2 and the electrode 23can be electrically coupled with each other at a lower resistance.

Second Embodiment

In First Embodiment, there has been shown the example where the dummyelectrode DE is formed, and the plug PG2 is electrically coupled withthe portion of the electrode 23 formed at the side surface of the dummyelectrode DE (see FIG. 3). On the other hand, in Second Embodiment, adescription will be given to an example where the dummy electrode DE isnot formed, and an opening OP2 is formed in the electrode 16, so thatthe plug PG2 is electrically coupled with the electrode 23 formed in theinside of the opening OP2 formed in the electrode 16 (see FIG. 35described later).

FIG. 34 is a plan view showing the capacitive element in SecondEmbodiment. FIG. 35 is a cross sectional view showing the capacitiveelement in Second Embodiment. FIG. 35 is a cross sectional view alongline A-A of FIG. 34. As shown in FIGS. 34 and 35, the semiconductordevice of the present Second Embodiment can be set equal to thesemiconductor device of First Embodiment except for the arrangement ofthe electrode 16, the electrode 23, the plug PG1, and the plug PG2.

As shown in FIGS. 34 and 35, the semiconductor device has the electrode16 formed of a conductive film CF1 formed over the element isolationregion 11, but, as distinct from First Embodiment, does not have thedummy electrode DE (see FIG. 3). On the other hand, the semiconductordevice has an opening OP2 penetrating through the electrode 16 asdistinct from First Embodiment. Then, the semiconductor device has theconductive film CF2 formed in the inside of the opening OP2, and theelectrode 23 formed of the conductive film CF2 integrally formed at thecircumferential side surface of the electrode 16. The electrode 23 isformed of the conductive film CF2 formed of, for example, a polysiliconfilm, and the metal silicide film 33 formed of, for example, a cobaltsilicide film formed at the surface of the conductive film CF2.

Incidentally, as with First Embodiment, between the electrode 16 and theelectrode 23, there is formed a capacitive insulation film 27 formed ofa insulation film IF2. Then, the electrode 16, the electrode 23, and thecapacitive insulation film 27 form the capacitive element. An interlayerinsulation film 34 is formed in such a manner as to cover the capacitiveelement formed of the electrode 16, the electrode 23, and the capacitiveinsulation film 27. In the interlayer insulation film 34, there areformed contact holes CH1 and CH2 as coupling holes.

The contact hole CH1 penetrates through the interlayer insulation film34, and reaches the electrode 16. The plug PG1 is formed of a conductivefilm embedded in the contact hole CH1, and is electrically directlycoupled with the electrode 16.

The contact hole CH2 penetrates through the interlayer insulation film34, and reaches the electrode 23. The plug PG2 is formed of a conductivefilm embedded in the contact hole CH2, and is electrically directlycoupled with the electrode 23. With such a configuration, the plug PG2formed of a conductive film embedded in the contact hole CH2 can beelectrically coupled with any portion of the electrode 23 via the metalsilicide film 33 formed at the surface of the electrode 23, and having arelatively smaller electric resistance. For this reason, the plug PG2can be electrically coupled with any portion of the electrode 23 at alow resistance.

Also in the present Second Embodiment, the electrode 16 and theelectrode 23 are formed in different regions in plan view. Such aconfiguration eliminates a fear that the contact hole CH2 penetratesthrough the electrode 23 and reaches the electrode 16. This can preventan electric short circuit between the electrode 23 and the electrode 16via the plug PG2.

Preferably, the semiconductor device has a plurality of openings OP2penetrating through the electrode 16, and the electrode 23 formed ineach inside of the plurality of openings OP2. The plurality of openingsOP2 respectively extend in the Y axis direction, and are arrayed in theX axis direction. Thus, the semiconductor device has the plurality ofopenings OP2 penetrating through the electrode 16, and the electrode 23formed in each inside of the plurality of openings OP2. This results ina larger area of the side surface of the electrode 23 opposite to theside surface of the electrode 16. For this reason, it is possible toincrease the capacity of the capacitive element with ease.

Incidentally, as with First Embodiment, when the conductive film CF1 ispatterned, the opening 022 is prevented from penetrating through theconductive film CF1. This is also applicable to Second Embodiment andrespective modified examples of Second Embodiment. At this step, thesemiconductor device has the opening OP2 formed in the electrode 16.

FIRST MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 36 is a plan view showing the capacitive element in the firstmodified example of Second Embodiment. FIG. 37 is a cross sectional viewshowing the capacitive element of the first modified example of SecondEmbodiment. FIG. 37 is a cross sectional view along line A-A of FIG. 36.

The capacitive element in the present first modified example isdifferent from the capacitive element in Second Embodiment described byreference to FIGS. 34 and 35 in that the electrode 23 is formed not onlyin the inside of each opening OP2 penetrating through the electrode 16,and the circumferential side surface of the electrode 16 but also in apartial region of the top surface of the electrode 16. The capacitiveelement in the present first modified example is the same as thecapacitive element in Second Embodiment in other respects.

As shown in FIG. 36, the electrode 16 has a rectangular shape in planview, and is integrally formed. Incidentally, also in the present firstmodified example, as with Second Embodiment, the dummy electrode DE (seeFIG. 3) is not formed.

The electrodes 23 are also formed in a partial region of the top surfaceof the electrode 16 in addition to the insides of the openings OP2, andthe circumferential side surface of the electrode 16. Further, at theside surface of the portion of the electrode 23 formed over the topsurface of the electrode 16, there is formed a sidewall 29 c formed ofan insulation film.

In the present first modified example, each contact hole CH2 penetratesthrough the interlayer insulation film 34, and reaches the electrode 23in a region overlapping the opening OP2 in plan view. Further, the plugPG2 formed of a conductive film embedded in the contact hole CH2 iselectrically coupled with the electrode 23 in the region overlapping theopening OP2 in plan view. As a result, even when the contact hole CH2penetrates through the interlayer insulation film 34, so that theelectrode 23 is overetched, the contact hole CH2 can be prevented frompenetrating through the capacitive insulation film 27, and reaching theelectrode 16. This can prevent the plug PG2 formed of a conductive filmembedded in the contact hole CH2 from causing a short circuit betweenthe electrode 16 and the electrode 23. For this reason, the performanceof the semiconductor device can be improved.

Also in the present first modified example, as with Second Embodiment,the plug PG2 can be electrically coupled with any portion of theelectrode 23. This can prevent an electric short circuit between theelectrode 16 and the electrode 23. Accordingly, the contact hole CH2 canbe aligned with ease.

On the other hand, in the first modified example, as compared withSecond Embodiment, the top surface of the electrode 16 and the bottomsurface of the electrode 23 are opposite to each other. For this reason,the capacity of the capacitive element can be increased with ease.

Then, a description will be given to the case where the ratio of thethickness of the conductive film CF2 forming the electrode 23 to theopen width of the opening OP2 is changed.

FIG. 38 is a plan view showing a capacitive element in a still otherexample. FIGS. 39 and 40 are each a cross sectional view showing acapacitive element in a still other example. FIGS. 39 and 40 are each across sectional view along line A-A of FIG. 38.

Incidentally, in the example shown in FIGS. 38 to 40, a description willbe given to the case where tow openings OP2 penetrating through theelectrode 16 are formed.

The open width of the opening OP2 is referred to as open width WT1, andthe thickness of the conductive film CF2 forming the electrode 23 isreferred to as thickness TH1. Then, in the example shown in FIG. 39, thefollowing expression (1) is assumed to hold:

WT1≦2×TH1   Expression (1).

In this case, as shown in FIG. 39, the inside of the opening OP2 can befilled with the conductive film CF2. When the inside of the opening OP2is thus filled with the conductive film CF2, the plug PG2 formed of aconductive film embedded in the contact hole CH2 penetrating through theinterlayer insulation film 34, and reaching the electrode 23 in theregion overlapping the opening OP2 in plan view is electrically coupledwith the electrode 23 in the region overlapping the opening OP2 in planview. As a result, even when the contact hole CH2 penetrates through theinterlayer insulation film 34, so that the electrode 23 is overetched,it is possible to prevent a short circuit between the electrode 16 andthe electrode 23 through the plug PG2 formed of a conductive filmembedded in the contact hole CH2. For this reason, the performance ofthe semiconductor device can be improved.

Incidentally, in FIG. 39, the open width WT1 of the opening OP2 is shownas the open width with the capacitive insulation film 27 formed at theside surface of the opening OP2 (the same also applies to FIG. 40).

On the other hand, even when the open width WT1 and the thickness TH1 ofthe conductive film do not satisfy the expression (1), as shown in FIG.40, each gap of the conductive film CF2 can be further filled with asidewall 29 d formed of an insulation film. Herein, the thickness of theinsulation film forming the sidewall 29 d is set at thickness TH2 equalto the thickness of the insulation film forming the sidewall 29 c. Inthis case, in the example shown in FIG. 40, the following expression (2)is assume to hold:

2×TH1<WT1≦2×(TH1+TH2)   Expression (2)

In this case, as shown in FIG. 40, the conductive film CF2 is formed atthe side surface and the bottom surface of the opening OP2. Theinsulation film forming the sidewall 29 d is formed in the inside of theopening OP2 and over the conductive film CF2. For this reason, theinside of the opening OP2 can be filled with the sidewall 29 d via theconductive film CF2. Even when the inside of the opening OP2 is filledwith the sidewall 29 d via the conductive film CF2, the plug PG2embedded in the contact hole CH2 penetrating through the interlayerinsulation film 34, and reaching the electrode 23 in the regionoverlapping the opening OP2 in plan view is electrically coupled withthe electrode 23 in the region overlapping the opening OP2 in plan view.As a result, even when the contact hole CH2 penetrates through theinterlayer insulation film 34, so that the electrode 23 is overetched,it is possible to prevent a short circuit between the electrode 16 andthe electrode 23 through the plug PG2 formed of a conductive filmembedded in the contact hole CH2. For this reason, the performance ofthe semiconductor device can be improved.

SECOND MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 41 is a plan view showing a capacitive element in a second modifiedexample of Second Embodiment. FIG. 42 is a cross sectional view showingthe capacitive element in the second modified example of SecondEmbodiment. FIG. 42 is a cross sectional view along line A-A of FIG. 41.

The capacitive element of the present second modified example isdifferent from the semiconductor device of Second Embodiment describedby reference to FIGS. 34 and 35 in that a cap insulation film CP1 isformed in a partial region of the top surface of the electrode 16. Inother respective, the capacitive element of the present second modifiedexample is the same as the capacitive element in Second Embodiment.

As shown in FIGS. 41 and 42, over the portion of the electrode 16arranged in the region surrounding the openings OP2, there is formed thecap insulation film CP1. The cap insulation film CP1 is formed of aninsulation film IF3 such as a silicon nitride film.

Incidentally, in the region of the top surface of the electrode 16 inwhich the cap insulation film CP1 is formed, there is not formed themetal silicide film 33. On the other hand, in the region of the topsurface of the electrode 16 in the vicinity of the plugs PG1, the metalsilicide film 33 is formed, but the cap insulation film CP1 is notformed.

Also in the present second modified example, as with Second Embodiment,the plug PG2 can be coupled with any portion of the electrode 23 at alow resistance. Thus, it is possible to prevent an electric shortcircuit between the electrode 16 and the electrode 23 through the plugPG2. As a result, the capacity of the capacitive element can beincreased with ease.

On the other hand, in the present second modified example, the region ofthe electrode 16 in contact with the electrode 23 via the capacitiveinsulation film 27 in plan view is covered with the cap insulation filmCP1. Therefore, in the present second modified example, as compared withSecond Embodiment, an electric short circuit between the electrode 16and the electrode 23 can be prevented with more reliability.

<Method for Manufacturing a Semiconductor Device>

As for the method for manufacturing the semiconductor device of thepresent Second Embodiment, there can be performed the same steps as thesteps described by reference to FIGS. 14 to 16, 20 to 22, 25 to 31, and12 in First Embodiment.

However, in the present Second Embodiment, when the conductive film CF1is patterned in the same step as the step described by reference to FIG.16, the openings OP2 (see FIG. 35) are formed. Further, in the same stepas the step described by reference to FIG. 20, the insulation film IF2is formed over the semiconductor substrate 10 including the inside ofeach opening OP2, and the surface of the electrode 16. Whereas, in thesame step as the step described by reference to FIG. 22, the conductivefilm CF2 is etched back. As a result, the conductive film CF1 is left atthe inside of each opening OP2 and the circumferential side surface ofthe electrode 16 via the insulation film IF2. Further, in the same stepas the step described by reference to FIG. 12, the contact hole CH2 isformed in such a manner as to penetrate through the interlayerinsulation film 34, and to reach the electrode 23 formed in the insideof the opening OP2 in the region overlapping the opening OP2 in planview, and the plug PG2 is electrically coupled with the electrode 23formed in the inside of each opening OP2.

<Main Feature and Effect of the Present Embodiment>

In the present Second Embodiment, the electrode 23 is formed in eachinside of the openings OP2 penetrating through the electrode 16. Then,in the present Second Embodiment, as with First Embodiment, the plug PG2formed of a conductive film embedded in the contact hole CH2 penetratesthrough the interlayer insulation film 34, and is electrically coupledwith the electrode 23 formed in the inside of the opening OP2. At thesurface of the electrode 23 formed in the inside of each opening, thereis formed the metal silicide film 33. With such a configuration, theplug PG2 can be electrically coupled with any portion of the electrode23 formed in the inside of each opening OP2 via the metal silicide film33 with a relatively smaller electric resistance formed at the surfaceof the electrode 23. For this reason, the plug PG2 can be coupled withany portion of the electrode 23 formed in the inside of each opening OP2at a low resistance.

Further, in the present Second Embodiment, the electrode 23 formed inthe inside of each opening OP2 does not overlap the electrode 16 in planview. Therefore, the contact hole CH2 does not penetrate through theinterlayer insulation film 34, the electrode 23, and the capacitiveinsulation film 27 to reach the electrode 16, and the plug PG2 formed ofa conductive film embedded in the contact hole CH2 does not cause ashort circuit between the electrode 23 and the electrode 16.Accordingly, the performance of the semiconductor device can beimproved.

Third Embodiment

In First Embodiment, there has been shown the example where the dummyelectrode DE is formed, and the plug PG2 is electrically coupled withthe portion of the electrode 23 formed at the side surface of the dummyelectrode DE (see FIG. 3). On the other hand, in Third Embodiment, adescription will be given to an example where the dummy electrode DE isnot formed, and each plug PG3 is electrically coupled with the portionof the electrode 23 arranged between adjacent line parts LP1 (see FIG.43 described later).

FIG. 43 is a plan view showing a capacitive element in Third Embodiment.Incidentally, the cross sectional view along line A-A of FIG. 43 is thesame as the cross sectional view of the capacitive element in the firstmodified example of First Embodiment described by reference to FIG. 5.As shown in FIGS. 43 and 5, the capacitive element of the present ThirdEmbodiment can be set equal to the capacitive element in the firstmodified example of First Embodiment except that the dummy electrode DE(see FIG. 3) is not formed.

Therefore, in the present Third Embodiment, the plug PG2 in the firstmodified example of First Embodiment (see FIG. 4) is not formed, andonly the plugs PG1 and the plugs PG3 are formed.

Also in the present Third Embodiment, as with First Embodiment, eachplug PG3 can be electrically coupled with the portion of the electrode23 arranged between the adjacent line parts LP1 at a low resistance.This can prevent an electric short circuit between the electrode 16 andthe electrode 23. Accordingly, the capacity of the capacitive elementcan be increased with ease.

On the other hand, in the present Third Embodiment, as with the firstmodified example of First Embodiment, as compared with First Embodiment,the width of the line part LP1 becomes larger, but the plug PG1 can beelectrically directly coupled with the line part. For this reason, theplug PG1 can be electrically coupled with the electrode 16 at a stilllower resistance.

Incidentally, as with First Embodiment, when the conductive film CF1 ispatterned, the opening OP1 formed between the adjacent line parts LP1(see FIG. 6) is prevented from penetrating through the conductive filmCF1. This is also applicable to Third Embodiment and respective modifiedexamples of Third Embodiment. In this case, the electrode 16 includesthe coupling, part CN1 coupling the bottoms of the adjacent line partsLP1 as shown in FIG. 6.

FIRST MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 44 is a plan view showing a capacitive element in a first modifiedexample of Third Embodiment. Incidentally, the cross sectional viewalong line A-A of FIG. 44 is the same as the cross sectional view of thecapacitive element of the first modified example of First Embodimentdescribed by reference to FIG. 5.

The capacitive element in the present first modified example isdifferent from the capacitive element in Third Embodiment described byreference to FIG. 43 in that the line part LP2 is disposed, and in thatthe plurality of plugs PG1 are electrically directly coupled with notonly respective ones of the plurality of line parts LP1 but also theline part LP2. In other respects, the capacitive element in the presentfirst modified example is the same as the capacitive element in ThirdEmbodiment.

As shown in FIG. 44, the electrode 16 includes the plurality of lineparts LP1 and the line part LP2. The plurality of line parts LP1respectively extend in the Y axis direction, and are arrayed in the Xaxis direction, in plan view. The line part LP2 extends in the X axisdirection, and is coupled with the ends on one side of the plurality ofline parts LP1 in the Y axis direction in plan view. With such aconfiguration, the plurality of line parts LP1 are electrically coupledto one another via the line part LP2. The electrode 16 including theplurality of line parts LP1 and the line part LP2 has a comb-like shapein plan view.

The contact holes CH1 penetrate through the interlayer insulation film34 (see FIG. 5), and reach not only the plurality of line parts LP1 butalso the line part LP2. The plugs PG1 are each formed of a conductivefilm embedded in each contact hole CH1, and are electrically coupledwith not only the plurality of line parts LP1 but also the line partLP2.

Also in the present first modified example, as with Third Embodiment,the plugs PG3 can be electrically coupled with any portion of theelectrode 23 at a low resistance. This can prevent an electric shortcircuit between the electrode 16 and the electrode 23. Accordingly, thecapacity of the capacitive element can be increased with ease.

On the other hand, in the present first modified example, as comparedwith Third Embodiment, the area of the side surface of the electrode 23opposite to the side surface of the electrode 16 increases. For thisreason, the capacity of the capacitive element can be increased withease. Further, in the present first modified example, as compared withThird Embodiment, the number of the plugs PG1 electrically directlycoupled with the electrode 16 increases. For this reason, the plugs PG1can be electrically coupled with the electrode 16 at a still lowerresistance.

SECOND MODIFIED EXAMPLE OF CAPACITIVE ELEMENT

FIG. 45 is a plan view showing a capacitive element in a second modifiedexample of Third Embodiment. FIG. 46 is a cross sectional view showingthe capacitive element in the second modified example of ThirdEmbodiment. FIG. 46 is a cross sectional view along line A-A of FIG. 45.

The capacitive element of the present second modified example isdifferent from the capacitive element in the first modified example ofThird Embodiment described by reference to FIGS. 44 and 45 in that a capinsulation film CP1 is formed in a partial region of the top surface ofthe electrode 16. In other respects, the capacitive element of thepresent second modified example is the same as the capacitive element inthe first modified example of Third Embodiment.

As shown in FIGS. 45 and 46, the cap insulation film CP1 is formed atleast in a region in contact with the electrode 23 via the capacitiveinsulation film 27 in plan view over the line parts LP1, and over a partof the line part LP2, namely, over a part of the electrode 16. The capinsulation film CP1 is formed of an insulation film IF3 such as asilicon nitride film.

Incidentally, in the region of the top surface of each line part LP1 inwhich the cap insulation film CP1 is formed, there is not formed themetal silicide film 33. On the other hand, in the region of the topsurface of the line part LP2 in the vicinity of the plug PG1, there isformed the metal silicide film 33, but there is not formed the capinsulation film CP1.

Further, in the present second modified example, the metal silicide film33 is not formed over the line parts LP1. For this reason, the plugs PG1are not electrically directly coupled with the line parts LP1, and areelectrically directly coupled with the line part LP2.

Also in the present second modified example, as with the first modifiedexample of Third Embodiment, the plugs PG3 can be electrically coupledwith any portion of the electrode 23 at a low resistance. Thus, it ispossible to prevent an electric short circuit between the electrode 16and the electrode 23 through the plugs PG3. Accordingly, the capacity ofthe capacitive element can be increased with ease.

On the other hand, in the present second modified example, the region ofthe electrode 16 in contact with the electrode 23 via the capacitiveinsulation film 27 in plan view is covered with the cap insulation filmCP1. Therefore, in the present second modified example, as compared withthe first modified example of Third Embodiment, it is possible toprevent an electric short circuit between the electrode 16 and theelectrode 23 adjacent to each other with more reliability.

<Method for Manufacturing a Semiconductor Device>

As for the method for manufacturing the semiconductor device of thepresent Third Embodiment, there can be performed the same steps as thesteps described by reference to FIGS. 14 to 16, 20 to 22, 25 to 31, and12 in First Embodiment.

However, in the present Third Embodiment, when the conductive film CF1is patterned in the same step as the step described by reference to FIG.16, the dummy electrode DE (see FIG. 16) is not formed, and theelectrode 16 including a plurality of line parts LP1 respectivelyextending in the Y axis direction, and arrayed in the X axis direction(see FIG. 43) is formed of the conductive film CF1. Further, in the samestep as the step described by reference to FIG. 20, the dummy electrodeDE (see FIG. 16) is not formed. For this reason, over the semiconductorsubstrate 10 including the surface of the electrode 16, there is formedan insulation film IF2. Further, in the same step as the step describedby reference to FIG. 22, the dummy electrode DE (see FIG. 22) is notformed. For this reason, the conductive film CF2 is etched back, therebyto leave the conductive film CF1 at the circumferential side surface ofthe electrode 16 via the insulation film IF2. Furthermore, in the samestep as the step described by reference to FIG. 12, the contact holesCH3 are formed in such a manner as to penetrate through the interlayerinsulation film 34, and to reach the portion of the electrode 23arranged between the adjacent line parts LP1. Thus, the plugs PG3 areelectrically coupled with the portion of the electrode 23 arrangedbetween the adjacent line parts LP1.

<Main Feature and Effect of the Present Embodiment>

In the present Third Embodiment, as with First Embodiment, the contactplug PG3 formed of a conductive film embedded in each contact hole CH3penetrates through the interlayer insulation film 34, and iselectrically directly coupled with the portion of the electrode 23arranged between the adjacent line parts LP1. At the portion of theelectrode 23 arranged between the adjacent line parts LP1, there isformed the metal silicide film 33. With such a configuration, the plugsPG3 can be electrically coupled with any portion of the electrode 23 viathe metal silicide film 33 with a relatively smaller electric resistanceformed at the surface of the electrode 23. For this reason, the plugsPG3 can be electrically coupled with any portion of the electrode 23 ata low resistance.

Further, in the present Third Embodiment, the electrode 23 does notoverlap the electrode 16 in plan view. Therefore, the contact holes CH3do not penetrate through the interlayer insulation film 34, theelectrode 23, and the capacitive insulation film 27 to reach theelectrode 16. Further, the electrode 23 and the electrode 16 are notshort-circuited through the plugs PG3 formed of a conductive filmembedded in the contact holes CH3. Accordingly, the performance of thesemiconductor device can be improved.

Fourth Embodiment

In First Embodiment, there has been shown the example in which onecapacitive element is formed over the element isolation region. InFourth Embodiment, a description will be given to the configuration inwhich a plurality of capacitive elements are formed over a conductivesemiconductor substrate.

The plan layout of the capacitive elements in the present FourthEmbodiment is the same as the plan layout of the capacitive elements inFirst Embodiment described by reference to FIG. 2. The differencesbetween the present Fourth Embodiment and First Embodiment appear in thecross sectional view.

FIG. 47 is a cross sectional view of the capacitive element in FourthEmbodiment. FIG. 47 corresponds to the cross sectional view along lineA-A of FIG. 2.

As shown in FIG. 47, in the semiconductor substrate 10, there are formedelement isolation regions 11. In an active region interposed between theelement isolation regions 11, there is formed a capacitive element.Namely, the semiconductor device of the present Fourth Embodiment has alower electrode including the semiconductor substrate 10 as anelectrode, a capacitive insulation film 14 including an insulation filmIF1 formed over the semiconductor substrate 10, and an upper electrodeincluding an electrode 16 formed over the capacitive insulation film 14.Then, the lower electrode including the semiconductor substrate 10 as anelectrode, the capacitive insulation film 14, and the upper electrodeincluding the electrode 16 form a first capacitive element.

Further, as with First Embodiment, the electrode 16, the capacitiveinsulation film 27, and the electrode 23 form a second capacitiveelement.

Incidentally, although not shown, the lower electrode including thesemiconductor substrate 10 as an electrode, the capacitive insulationfilm 27, and the upper electrode including the electrode 23 also canform a third capacitive element.

The method for manufacturing a semiconductor device in the presentFourth Embodiment is the same as the method for manufacturing acapacitive element in First Embodiment except that the capacitiveelement is formed over the semiconductor substrate 10 as an activeregion interposed between the element isolation regions 11.

In the present Fourth Embodiment, the first capacitive element and thesecond capacitive element are formed. Therefore, the first capacitiveelement and the second capacitive element are coupled in parallel witheach other. As a result, it is possible to form a capacitive elementequal in occupying area to and larger in capacity value than in FirstEmbodiment. The parallel coupling of the first capacitive element andthe second capacitive element can be achieved by setting thesemiconductor substrate 10 and the electrode 23 at the same electricpotential.

Incidentally, in the present Fourth Embodiment, the capacitive elementof First Embodiment is formed not over the element isolation region 11,but over the semiconductor substrate 10 interposed between the elementisolation regions 11. However, the present Fourth Embodiment is alsoapplicable to the cases where each capacitive element in respectiveembodiments and respective modified examples of the embodimentsincluding First Embodiment is formed not over the element isolationregion 11 but over the semiconductor substrate 10 interposed between theelement isolation regions 11.

Up to this point, the invention made by the present inventors wasspecifically described by way of embodiments. However, it is naturallyunderstood that the present invention is not limited to the embodiments,and may be variously changed within the scope not departing from thegist thereof.

The present invention includes at least the following embodiments.

[Additional Statement 1]

A method for manufacturing a semiconductor device, including the stepsof:

(a) forming a first conductive film over a semiconductor substrate,

(b) patterning the first conductive film, and forming a first electrodeformed of the first conductive film, and forming a first dummy electrodeformed of the first conductive film apart from the first electrode,

(c) forming a first insulation film over the semiconductor substrateincluding the surface of the first electrode and the surface of thefirst dummy electrode,

(d) forming a second conductive film over the first insulation film,

(e) etching back the second conductive film, and leaving the secondconductive film between the first electrode and the first dummyelectrode, at the circumferential side surface of the first electrode,and at the circumferential side surface of the first dummy electrode viathe first insulation film, thereby to form a second electrode,

(f) removing a portion of the first insulation film not covered with thesecond electrode, and forming a first capacitive insulation film formedof the first insulation film between the first electrode and the secondelectrode,

(g) forming an interlayer insulation film in such a manner as to coverthe first electrode, the second electrode, and the first capacitiveinsulation film,

(h) forming a first coupling hole penetrating through the interlayerinsulation film, and reaching the first electrode, and a second couplinghole penetrating through the interlayer insulation film, and reaching afirst portion of the second electrode formed at a side surface of thefirst dummy electrode opposite to the first electrode side, and

(i) forming a first coupling electrode formed of a third conductive filmembedded in the first coupling hole, and electrically coupled with thefirst electrode, and forming a second coupling electrode formed of thethird conductive film embedded in the second coupling hole, andelectrically coupled with the first portion of the second electrode,

wherein in the step (f), the first electrode, the second electrode, andthe first capacitive insulation film form a first capacitive element.

[Additional Statement 2]

The method for manufacturing a semiconductor device according toAdditional Statement 1,

wherein in the step (e), the second conductive film is patterned andetched back, and thereby the second conductive film is left between thefirst electrode and the first dummy electrode, at the circumferentialside surface of the first electrode, at the circumferential side surfaceof the first dummy electrode, and in a partial region of the top surfaceof the first electrode via the first insulation film, thereby to formthe second electrode.

[Additional Statement 3]

The method for manufacturing a semiconductor device according toAdditional Statement 1, including:

a step (j) of, after the step (f) and before the step (g), forming afirst metal silicide film at the surface of the first conductive film,and forming a second metal silicide film at the surface of the secondconductive film,

wherein, in the step (i), the first coupling electrode in contact withthe first metal silicide film is formed, and the second couplingelectrode in contact with the second metal silicide film is formed.

[Additional Statement 4]

The method for manufacturing a semiconductor device according toAdditional Statement 1, including:

a step (k) of, before the step (a), forming a second insulation film atthe first main surface of the semiconductor substrate in a first regionon the first main surface side of the semiconductor substrate, and in asecond region on the first main surface side of the semiconductorsubstrate,

wherein, in the step (a), the first conductive film is formed over thesecond insulation film in the first region and the second region,

wherein, in the step (b), the first conductive film and the secondinsulation film are patterned in the first region and the second region,and the first electrode and the first dummy electrode are formed in thefirst region, and a first gate electrode formed of the first conductivefilm, and a first gate insulation film formed of the second insulationfilm between the first gate electrode and the semiconductor substrateare formed in the second region,

wherein, in the step (c), the first insulation film is formed over thesemiconductor substrate including the surface of the first electrode,the surface of the first dummy electrode, and the surface of the firstgate electrode in the first region and the second region,

wherein, in the step (d), the second conductive film is formed over thefirst insulation film in the first region and the second region,

wherein, in the step (e), the second conductive film is etched back inthe first region and the second region, thereby to form the secondelectrode in the first region, and the second conductive film is left atthe side surface of the first gate electrode via the first insulationfilm, thereby to form a second gate electrode in the second region, and

wherein, in the step (f), a portion of the first insulation film notcovered with any of the second electrode and the second gate electrodeis removed in the first region and the second region, the firstcapacitive insulation film is formed in the first region, and a secondgate insulation film formed of the first insulation film between thefirst gate electrode and the second gate electrode, and the firstinsulation film between the second gate electrode and the semiconductorsubstrate is formed in the second region,

the method including:

a step (l) of, after the step (f) and before the step (g), forming asource region and a drain region in alignment with the first gateelectrode and the second gate electrode in the semiconductor substratein the second region,

wherein, in the step (g), the interlayer insulation film is formed insuch a manner as to cover the first electrode, the second electrode, thefirst capacitive insulation film, the first gate electrode, the secondgate electrode, the second gate insulation film, the source region, andthe drain region in the first region and the second region,

wherein, in the step (h), the first coupling hole and the secondcoupling hole are formed in the first region, and a third coupling holepenetrating through the interlayer insulation film, and reaching thesource region, and a fourth coupling hole penetrating through theinterlayer insulation film, and reaching the drain region are formed inthe second region,

wherein, in the step (i), the first coupling electrode and the secondcoupling electrode are formed in the first region, and a third couplingelectrode formed of the third conductive film embedded in the thirdcoupling hole, and electrically coupled with the source region isformed, and a fourth coupling electrode formed of the third conductivefilm embedded in the fourth coupling hole, and electrically coupled withthe drain region are formed in the second region, and

wherein, in the step (l), the first gate insulation film, the first gateelectrode, the second gate electrode, and the second gate insulationfilm form a memory cell.

[Additional Statement 5]

The method for manufacturing a semiconductor device according toAdditional Statement 1, including:

a step (m) of before the step (a), forming an element isolation regionin the semiconductor substrate,

wherein, in the step (a), the first conductive film is formed over theelement isolation region.

[Additional Statement 6]

A method for manufacturing a semiconductor device, including the stepsof:

(a) forming a first conductive film over a semiconductor substrate,

(b) patterning the first conductive film, and forming a first electrodeformed of the first conductive film, and a first opening penetratingthrough the first electrode,

(c) forming a first insulation film over the semiconductor substrateincluding the inside of the first opening, and the surface of the firstelectrode,

(d) forming a second conductive film over the first insulation film,

(e) etching back the second conductive film, and leaving the secondconductive film in the inside of the first opening, and at thecircumferential side surface of the first electrode, via the firstinsulation film, thereby to form a second electrode,

(f) removing a portion of the first insulation film not covered with thesecond electrode, and forming a first capacitive insulation film formedof the first insulation film between the first electrode and the secondelectrode,

(g) forming an interlayer insulation film in such a manner as to coverthe first electrode, the second electrode, and the first capacitiveinsulation film,

(h) forming a first coupling hole penetrating through the interlayerinsulation film, and reaching the first electrode, and a second couplinghole penetrating through the interlayer insulation film, and reachingthe second electrode, and

(i) forming a first coupling electrode formed of a third conductive filmembedded in the first coupling hole, and electrically coupled with thefirst electrode, and forming a second coupling electrode formed of thethird conductive film embedded in the second coupling hole, andelectrically coupled with the second electrode,

wherein, in the step (f), the first electrode, the second electrode, andthe first capacitive insulation film form a first capacitive element.

[Additional Statement 7]

A method for manufacturing a semiconductor device, including the stepsof:

(a) forming a first conductive film over a semiconductor substrate,

(b) patterning the first conductive film, and forming a first electrodeformed of the first conductive film,

(c) forming a first insulation film over the first semiconductorsubstrate including the surface of the first electrode,

(d) forming a second conductive film over the first insulation film,

(e) etching back the second conductive film, an leaving the secondconductive film at the circumferential side surface of the firstelectrode via the first insulation film, thereby to form a secondelectrode,

(f) removing a portion of the first insulation film not covered with thesecond electrode, and forming a first capacitive insulation film formedof the first insulation film between the first electrode and the secondelectrode,

(g) forming an interlayer insulation film in such a manner as to coverthe first electrode, the second electrode, and the first capacitiveinsulation film,

(h) forming a first coupling hole penetrating through the interlayerinsulation film, and reaching the first electrode, and a second couplinghole penetrating through the interlayer insulation film, and reachingthe second electrode, and

(i) forming a first coupling electrode formed of a third conductive filmembedded in the first coupling hole, and electrically coupled with thefirst electrode, and forming a second coupling electrode formed of thethird conductive film embedded in the second coupling hole, andelectrically coupled with the second electrode,

wherein, in the step (f), the first electrode, the second electrode, andthe first capacitive insulation film form a first capacitive element,and

wherein, in the step (b), the first electrode including a plurality offirst line parts respectively extending in a first direction, andarrayed in a second direction crossing with the first direction in planview is formed of the first conductive film.

[Additional Statement 8]

A semiconductor device including:

a semiconductor substrate;

a first electrode formed of a first conductive film formed over thesemiconductor substrate;

a first dummy electrode formed apart from the first electrode over thesemiconductor substrate, and formed of a second conductive film at thesame layer as the first conductive film;

a second electrode formed of a third conductive film formed between thefirst electrode and the first dummy electrode, at the circumferentialside surface of the first electrode, and at the circumferential sidesurface of the first dummy electrode;

a first capacitive insulation film formed of a first insulation filmformed between the first electrode and the second electrode;

an interlayer insulation film formed in such a manner as to cover thefirst electrode, the second electrode, and the first capacitiveinsulation film;

a first coupling hole penetrating through the interlayer insulationfilm, and reaching the first electrode;

a second coupling hole penetrating through the interlayer insulationfilm, and reaching a first portion of the second electrode formed at aside surface of the first dummy electrode opposite to the firstelectrode side;

a first coupling electrode formed of a fourth conductive film embeddedin the first coupling hole, and electrically coupled with the firstelectrode; and

a second coupling electrode formed of a fifth conductive film embeddedin the second coupling hole, and electrically coupled with the firstportion of the second electrode,

wherein the first electrode, the second electrode, and the firstcapacitive insulation film form a first capacitive element,

wherein the first electrode includes:

a plurality of first line parts respectively extending in a firstdirection, and arrayed in a second direction crossing with the firstdirection in plan view, and

a coupling part coupling the bottoms of the first line parts adjacent toone another, and

wherein the first dummy electrode extends in the second direction, andis arranged on one sides of the first line parts in the first direction.

[Additional Statement 9]

A semiconductor device, including:

a semiconductor substrate,

a first electrode formed of a first conductive film formed over thesemiconductor substrate,

a first opening formed in the first electrode,

a second electrode formed of a second conductive film formed in theinside of the first opening, and at the circumferential side surface ofthe first electrode,

a first capacitive insulation film formed of a first insulation filmformed between the first electrode and the second electrode,

an interlayer insulation film formed in such a manner as to cover thefirst electrode, the second electrode, and the first capacitiveinsulation film,

a first coupling hole penetrating through the interlayer insulationfilm, and reaching the first electrode,

a second coupling hole penetrating through the interlayer insulationfilm, and reaching a first portion of the second electrode formed in theinside of the first opening,

a first coupling electrode formed of a third conductive film embedded inthe first coupling hole, and electrically coupled with the firstelectrode, and

a second coupling electrode formed of a fourth conductive film embeddedin the second coupling hole, and electrically coupled with the firstportion of the second electrode,

wherein the first electrode, the second electrode, and the firstcapacitive insulation film form a first capacitive element.

[Additional Statement 10]

A semiconductor device, including:

a semiconductor substrate,

a first electrode formed of a first conductive film formed over thesemiconductor substrate,

a second electrode formed of a second conductive film formed at thecircumferential side surface of the first electrode,

a first capacitive insulation film formed between the first electrodeand the second electrode,

an interlayer insulation film formed in such a manner as to cover thefirst electrode, the second electrode, and the first capacitiveinsulation film,

a first coupling hole penetrating through the interlayer insulationfilm, and reaching the first electrode,

a second coupling hole penetrating through the interlayer insulationfilm, and reaching the second electrode,

a first coupling electrode formed of a third conductive film embedded inthe first coupling hole, and electrically coupled with the firstelectrode, and

a second coupling electrode formed of a fourth conductive film embeddedin the second coupling hole, and electrically coupled with the secondelectrode,

wherein the first electrode, the second electrode, and the firstcapacitive insulation film form a first capacitive element, and

wherein the first electrode includes:

a plurality of first line parts respectively extending in a firstdirection, and arrayed in a second direction crossing with the firstdirection in plan view, and

a coupling part coupling the bottoms of the adjacent first line partsadjacent to one another.

1-20. (canceled)
 21. A method for manufacturing a semiconductor device,including the steps of: (a) forming a first conductive film over asemiconductor substrate, (b) patterning the first conductive film, andforming a first electrode formed of the first conductive film, andforming a first dummy electrode formed of the first conductive filmapart from the first electrode, (c) forming a first insulation film overthe semiconductor substrate including the surface of the first electrodeand the surface of the first dummy electrode, (d) forming a secondconductive film over the first insulation film, (e) etching back thesecond conductive film, and leaving the second conductive film betweenthe first electrode and the first dummy electrode, at thecircumferential side surface of the first electrode, and at thecircumferential side surface of the first dummy electrode via the firstinsulation film, thereby to form a second electrode, (f) removing aportion of the first insulation film not covered with the secondelectrode, and forming a first capacitive insulation film formed of thefirst insulation film between the first electrode and the secondelectrode, (g) forming an interlayer insulation film in such a manner asto cover the first electrode, the second electrode, and the firstcapacitive insulation film, (h) forming a first coupling holepenetrating through the interlayer insulation film, and reaching thefirst electrode, and a second coupling hole penetrating through theinterlayer insulation film, and reaching a first portion of the secondelectrode formed at a side surface of the first dummy electrode oppositeto the first electrode side, and (i) forming a first coupling electrodeformed of a third conductive film embedded in the first coupling hole,and electrically coupled with the first electrode, and forming a secondcoupling electrode formed of the third conductive film embedded in thesecond coupling hole, and electrically coupled with the first portion ofthe second electrode, wherein in the step (f), the first electrode, thesecond electrode, and the first capacitive insulation film form a firstcapacitive element.
 22. The method for manufacturing a semiconductordevice according to claim 21, wherein in the step (e), the secondconductive film is patterned and etched back, and thereby the secondconductive film is left between the first electrode and the first dummyelectrode, at the circumferential side surface of the first electrode,at the circumferential side surface of the first dummy electrode, and ina partial region of the top surface of the first electrode via the firstinsulation film, thereby to form the second electrode.
 23. The methodfor manufacturing a semiconductor device according to claim 21,including: a step (j) of, after the step (f) and before the step (g),forming a first metal silicide film at the surface of the firstconductive film, and forming a second metal silicide film at the surfaceof the second conductive film, wherein, in the step (i), the firstcoupling electrode in contact with the first metal silicide film isformed, and the second coupling electrode in contact with the secondmetal silicide film is formed.
 24. The method for manufacturing asemiconductor device according to claim 21, including: a step (k) of,before the step (a), forming a second insulation film at the first mainsurface of the semiconductor substrate in a first region on the firstmain surface side of the semiconductor substrate, and in a second regionon the first main surface side of the semiconductor substrate, wherein,in the step (a), the first conductive film is formed over the secondinsulation film in the first region and the second region, wherein, inthe step (b), the first conductive film and the second insulation filmare patterned in the first region and the second region, and the firstelectrode and the first dummy electrode are formed in the first region,and a first gate electrode formed of the first conductive film, and afirst gate insulation film formed of the second insulation film betweenthe first gate electrode and the semiconductor substrate are formed inthe second region, wherein, in the step (c), the first insulation filmis formed over the semiconductor substrate including the surface of thefirst electrode, the surface of the first dummy electrode, and thesurface of the first gate electrode in the first region and the secondregion, wherein, in the step (d), the second conductive film is formedover the first insulation film in the first region and the secondregion, wherein, in the step (e), the second conductive film is etchedback in the first region and the second region, thereby to form thesecond electrode in the first region, and the second conductive film isleft at the side surface of the first gate electrode via the firstinsulation film, thereby to form a second gate electrode in the secondregion, and wherein, in the step (f), a portion of the first insulationfilm not covered with any of the second electrode and the second gateelectrode is removed in the first region and the second region, thefirst capacitive insulation film is formed in the first region, and asecond gate insulation film formed of the first insulation film betweenthe first gate electrode and the second gate electrode, and the firstinsulation film between the second gate electrode and the semiconductorsubstrate is formed in the second region, the method including: a step(l) of, after the step (f) and before the step (g), forming a sourceregion and a drain region in alignment with the first gate electrode andthe second gate electrode in the semiconductor substrate in the secondregion, wherein, in the step (g), the interlayer insulation film isformed in such a manner as to cover the first electrode, the secondelectrode, the first capacitive insulation film, the first gateelectrode, the second gate electrode, the second gate insulation film,the source region, and the drain region in the first region and thesecond region, wherein, in the step (h), the first coupling hole and thesecond coupling hole are formed in the first region, and a thirdcoupling hole penetrating through the interlayer insulation film, andreaching the source region, and a fourth coupling hole penetratingthrough the interlayer insulation film, and reaching the drain regionare formed in the second region, wherein, in the step (i), the firstcoupling electrode and the second coupling electrode are formed in thefirst region, and a third coupling electrode formed of the thirdconductive film embedded in the third coupling hole, and electricallycoupled with the source region is formed, and a fourth couplingelectrode formed of the third conductive film embedded in the fourthcoupling hole, and electrically coupled with the drain region are formedin the second region, and wherein, in the step (l), the first gateinsulation film, the first gate electrode, the second gate electrode,and the second gate insulation film form a memory cell.
 25. The methodfor manufacturing a semiconductor device according to claim 21,including: a step (m) of, before the step (a), forming an elementisolation region in the semiconductor substrate, wherein, in the step(a), the first conductive film is formed over the element isolationregion.
 26. A method for manufacturing a semiconductor device, includingthe steps of: (a) forming a first conductive film over a semiconductorsubstrate, (b) patterning the first conductive film, and forming a firstelectrode formed of the first conductive film, and a first openingpenetrating through the first electrode, (c) forming a first insulationfilm over the semiconductor substrate including the inside of the firstopening, and the surface of the first electrode, (d) forming a secondconductive film over the first insulation film, (e) etching back thesecond conductive film, and leaving the second conductive film in theinside of the first opening, and at the circumferential side surface ofthe first electrode, via the first insulation film, thereby to form asecond electrode, (f) removing a portion of the first insulation filmnot covered with the second electrode, and forming a first capacitiveinsulation film formed of the first insulation film between the firstelectrode and the second electrode, (g) forming an interlayer insulationfilm in such a manner as to cover the first electrode, the secondelectrode, and the first capacitive insulation film, (h) forming a firstcoupling hole penetrating through the interlayer insulation film, andreaching the first electrode, and a second coupling hole penetratingthrough the interlayer insulation film, and reaching the secondelectrode, and (i) forming a first coupling electrode formed of a thirdconductive film embedded in the first coupling hole, and electricallycoupled with the first electrode, and forming a second couplingelectrode formed of the third conductive film embedded in the secondcoupling hole, and electrically coupled with the second electrode,wherein, in the step (f), the first electrode, the second electrode, andthe first capacitive insulation film form a first capacitive element.27. A method for manufacturing a semiconductor device, including thesteps of: (a) forming a first conductive film over a semiconductorsubstrate, (b) patterning the first conductive film, and forming a firstelectrode formed of the first conductive film, (c) forming a firstinsulation film over the first semiconductor substrate including thesurface of the first electrode, (d) forming a second conductive filmover the first insulation film, (e) etching back the second conductivefilm, an leaving the second conductive film at the circumferential sidesurface of the first electrode via the first insulation film, thereby toform a second electrode, (f) removing a portion of the first insulationfilm not covered with the second electrode, and forming a firstcapacitive insulation film formed of the first insulation film betweenthe first electrode and the second electrode, (g) forming an interlayerinsulation film in such a manner as to cover the first electrode, thesecond electrode, and the first capacitive insulation film, (h) forminga first coupling hole penetrating through the interlayer insulationfilm, and reaching the first electrode, and a second coupling holepenetrating through the interlayer insulation film, and reaching thesecond electrode, and (i) forming a first coupling electrode formed of athird conductive film embedded in the first coupling hole, andelectrically coupled with the first electrode, and forming a secondcoupling electrode formed of the third conductive film embedded in thesecond coupling hole, and electrically coupled with the secondelectrode, wherein, in the step (f), the first electrode, the secondelectrode, and the first capacitive insulation film form a firstcapacitive element, and wherein, in the step (b), the first electrodeincluding a plurality of first line parts respectively extending in afirst direction, and arrayed in a second direction crossing with thefirst direction in plan view is formed of the first conductive film.